Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34;
From:   Frank Li <Frank.Li@nxp.com>
To:     manivannan.sadhasivam@linaro.org
Cc:     Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev,
        kw@linux.com, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
        linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org,
        minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org,
        roy.zang@nxp.com
Subject: [PATCH v4 2/4] PCI: layerscape: Add suspend/resume for ls1021a
Date:   Wed, 29 Nov 2023 16:44:10 -0500
Message-Id: <20231129214412.327633-3-Frank.Li@nxp.com>
In-Reply-To: <20231129214412.327633-1-Frank.Li@nxp.com>
References: <20231129214412.327633-1-Frank.Li@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?QQIXzHcnKIpgMT5GsAP1N7Gbbr77yE11RivSPl/MrDdttkzmcjYNl8iOzDVB?=
 =?us-ascii?Q?og5hMMfiO8yikUW95HbaTFZSRP8PrjREZLnKO9rkKKcNT8OGd/K2SzRU+JsO?=
 =?us-ascii?Q?dkIFywM0pnpWHwx+sham+YQ5qOO9gSe3bny+jHOpTiMQOEsRpRMRQOXuw5Wc?=
 =?us-ascii?Q?ZYIhEmalBhthuNxAAyGHvgoFQXrL/FiaJTXZfsscLGHLOgL4LA1FFoKvEr1W?=
 =?us-ascii?Q?xlBg6gqXNQYAkJdmuPDwWVmHXPJnujpNxRRXjR6OXL2DX593App9xgPCgXUi?=
 =?us-ascii?Q?y7bHRlLTM5YGEQEhLEg+bWq6YPGOgaBtXpcOYdmIVaS7sF6vEiRr4th4c+PR?=
 =?us-ascii?Q?8FnYDjmRinf2NVpY05QgYk/CvuNcwcV2ycg+Bqq4qL9LScVawyX8UZCLUEb0?=
 =?us-ascii?Q?xcgsCcPsoo4bmv8+1XKOLjnP3afhhSju7L/YD2SF49olxlLIIbqqGBAgB1yX?=
 =?us-ascii?Q?8ZlpdtC7pQMaP9aFwLAg4ReLjoJ1mUTdK7oyEnGRTouj/VYrNq5NNiqDoM3w?=
 =?us-ascii?Q?aOeIHtGR6CrIVGAv9ScJHguaSfBbIcCdOPc37jcTvT/YFKe+ui1zIpKRhLiK?=
 =?us-ascii?Q?OT4FM1PBQ/gDOo2NU3mYesW7jIVvQ8ntN8sVOZVRQmNbMtapvKfK7pmo/v9n?=
 =?us-ascii?Q?wbi4Q82EJpypcu0uShBi080bSsHwi/Un0E5gLbVKYWBoQDwghddVIW3VD80l?=
 =?us-ascii?Q?fR9yYqzu+QHvVL518Psz9RR0UpXv2QNUP2hjN9AgUSkPZrzjgqcSZ6ycaG6y?=
 =?us-ascii?Q?vxR3qdbragK/hzWDLa+bdB2lPCCPI4JiVxdwcHAH/tiJ7swrLfvZSKB1dzc/?=
 =?us-ascii?Q?szloye0uJdOnWUdVhnsd/rud/kERJqxeJgl9/snH5GCiChzlwtYf08P+3fIr?=
 =?us-ascii?Q?ARMF+kIVM5nGNwGMYQNPONK7sOfR/JDGLqwQcSMQNsrJKtxZ6cre0pyJQgmU?=
 =?us-ascii?Q?jhDOoV6MqGVqRImCal9Rel8XFsG6k3f95oB/y/izXqa/wgIoa/70hk2dvRkv?=
 =?us-ascii?Q?ApoRPBZ5gh1sr/vcsVbk5iEdH7arCTIYWeOTr740wLKnA0a9M6wv1qIoHsJK?=
 =?us-ascii?Q?IYApwotCzhcnipR+x3s2xA41A71J9CAEw52DmTJBI60PHUEqZlscMF05eNcj?=
 =?us-ascii?Q?Ok7FCPfqQW8uN5HV9i4FjntcTS7vr2HugA0ARYqaPV9aFZmpvckuvu7uD4TM?=
 =?us-ascii?Q?+CGeGUYZddkAGIqvqKLXmQ1HzwCr3QXPj3pyDUk/f4hUsFMH7EU8JR+9vd+X?=
 =?us-ascii?Q?FtmhMHEdZPAwHLfJRxC9Xeof9cpKB6otPfw7r1K+N179vie+tDNLYkL7OcpT?=
 =?us-ascii?Q?ZcpEuZEnSG7o1qBDaKgAu6zSFZjQeIl0XakZzKTMnfv8/bup/RHgXGzwWi01?=
 =?us-ascii?Q?kW/JaZn308SR3vuTuiOfok22N9kRJKtggDnmo6yaVuOOqMyddw0xL5r564PM?=
 =?us-ascii?Q?lFfffrCzehBDHM6T/ProqRTryzXw0AZX7/Fe7jLtg9zMnvdpB6/WriCuUmCm?=
 =?us-ascii?Q?BPAn+T/Wqa0ZTb1o9fvOaQEmEORbAv7vJfI2fke0zMOyaJrahAdFKGZ0xsw8?=
 =?us-ascii?Q?6+6yQpk2GwCRHu4MjwM+d1DngbTA+E0yfs0C8IrT?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 9fb2c528-951d-4f01-d89b-08dbf1246216
X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2023 21:44:37.1656
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: +89MQHUZpGJc5fmQw6UpVSwTmh++KcHoXi8I9/hpOUP19WU2+B0lZb5FVR8NitOzTjGH32xVIXWNiJXOhK6fMg==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBAPR04MB7416
X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID,
	DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,
	SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable
	autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 29 Nov 2023 13:45:09 -0800 (PST)

ls1021a add suspend/resume support.

In the suspend path, PME_Turn_Off message is sent to the endpoint to
transition the link to L2/L3_Ready state. In this SoC, there is no way to
check if the controller has received the PME_To_Ack from the endpoint or
not. So to be on the safer side, the driver just waits for
PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF
bit to complete the PME_Turn_Off handshake. This link would then enter
L2/L3 state depending on the VAUX supply.

In the resume path, the link is brought back from L2 to L0 by doing a
software reset.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---

Notes:
    Change from v3 to v4
    - update commit message.
    - it is reset a glue logic part for PCI controller.
    - use regmap_write_bits() to reduce code change.
    
    Change from v2 to v3
    - update according to mani's feedback
    change from v1 to v2
    - change subject 'a' to 'A'

 drivers/pci/controller/dwc/pci-layerscape.c | 83 ++++++++++++++++++++-
 1 file changed, 82 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
index aea89926bcc4f..42bca2c3b5c3e 100644
--- a/drivers/pci/controller/dwc/pci-layerscape.c
+++ b/drivers/pci/controller/dwc/pci-layerscape.c
@@ -35,11 +35,19 @@
 #define PF_MCR_PTOMR		BIT(0)
 #define PF_MCR_EXL2S		BIT(1)
 
+/* LS1021A PEXn PM Write Control Register */
+#define SCFG_PEXPMWRCR(idx)	(0x5c + (idx) * 0x64)
+#define PMXMTTURNOFF		BIT(31)
+#define SCFG_PEXSFTRSTCR	0x190
+#define PEXSR(idx)		BIT(idx)
+
 #define PCIE_IATU_NUM		6
 
 struct ls_pcie_drvdata {
 	const u32 pf_off;
+	const struct dw_pcie_host_ops *ops;
 	int (*exit_from_l2)(struct dw_pcie_rp *pp);
+	bool scfg_support;
 	bool pm_support;
 };
 
@@ -47,6 +55,8 @@ struct ls_pcie {
 	struct dw_pcie *pci;
 	const struct ls_pcie_drvdata *drvdata;
 	void __iomem *pf_base;
+	struct regmap *scfg;
+	int index;
 	bool big_endian;
 };
 
@@ -171,13 +181,65 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp)
 	return 0;
 }
 
+static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask)
+{
+	/* Send PME_Turn_Off message */
+	regmap_write_bits(scfg, reg, mask, mask);
+
+	/*
+	 * There is no specific register to check for PME_To_Ack from endpoint.
+	 * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US.
+	 */
+	mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000);
+
+	/*
+	 * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit
+	 * to complete the PME_Turn_Off handshake.
+	 */
+	regmap_write_bits(scfg, reg, mask, 0);
+}
+
+static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+
+	scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF);
+}
+
+static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask)
+{
+	/* Only way exit from l2 is that do software reset */
+	regmap_write_bits(scfg, reg, mask, mask);
+
+	regmap_write_bits(scfg, reg, mask, 0);
+
+	return 0;
+}
+
+static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+
+	return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index));
+}
+
 static const struct dw_pcie_host_ops ls_pcie_host_ops = {
 	.host_init = ls_pcie_host_init,
 	.pme_turn_off = ls_pcie_send_turnoff_msg,
 };
 
+static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = {
+	.host_init = ls_pcie_host_init,
+	.pme_turn_off = ls1021a_pcie_send_turnoff_msg,
+};
+
 static const struct ls_pcie_drvdata ls1021a_drvdata = {
-	.pm_support = false,
+	.pm_support = true,
+	.scfg_support = true,
+	.ops = &ls1021a_pcie_host_ops,
+	.exit_from_l2 = ls1021a_pcie_exit_from_l2,
 };
 
 static const struct ls_pcie_drvdata layerscape_drvdata = {
@@ -205,6 +267,8 @@ static int ls_pcie_probe(struct platform_device *pdev)
 	struct dw_pcie *pci;
 	struct ls_pcie *pcie;
 	struct resource *dbi_base;
+	u32 index[2];
+	int ret;
 
 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
 	if (!pcie)
@@ -220,6 +284,7 @@ static int ls_pcie_probe(struct platform_device *pdev)
 	pci->pp.ops = &ls_pcie_host_ops;
 
 	pcie->pci = pci;
+	pci->pp.ops = pcie->drvdata->ops ? pcie->drvdata->ops : &ls_pcie_host_ops;
 
 	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
@@ -230,6 +295,22 @@ static int ls_pcie_probe(struct platform_device *pdev)
 
 	pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off;
 
+	if (pcie->drvdata->scfg_support) {
+		pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg");
+		if (IS_ERR(pcie->scfg)) {
+			dev_err(dev, "No syscfg phandle specified\n");
+			return PTR_ERR(pcie->scfg);
+		}
+
+		ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2);
+		if (ret) {
+			pcie->scfg = NULL;
+			return ret;
+		}
+
+		pcie->index = index[1];
+	}
+
 	if (!ls_pcie_is_bridge(pcie))
 		return -ENODEV;
 
-- 
2.34.1