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Thu, 30 Nov 2023 08:29:24 +0000 Received: from IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::55b:c350:980:ad8]) by IA1PR20MB4953.namprd20.prod.outlook.com ([fe80::55b:c350:980:ad8%6]) with mapi id 15.20.7046.024; Thu, 30 Nov 2023 08:29:24 +0000 From: Inochi Amaoto To: Yu-Chien Peter Lin Cc: Inochi Amaoto , Guo Ren , acme@kernel.org, adrian.hunter@intel.com, ajones@ventanamicro.com, alexander.shishkin@linux.intel.com, andre.przywara@arm.com, anup@brainfault.org, aou@eecs.berkeley.edu, atishp@atishpatra.org, conor+dt@kernel.org, conor.dooley@microchip.com, conor@kernel.org, devicetree@vger.kernel.org, dminus@andestech.com, evan@rivosinc.com, geert+renesas@glider.be, heiko@sntech.de, irogers@google.com, jernej.skrabec@gmail.com, jolsa@kernel.org, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-sunxi@lists.linux.dev, locus84@andestech.com, magnus.damm@gmail.com, mark.rutland@arm.com, mingo@redhat.com, n.shubin@yadro.com, namhyung@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, peterz@infradead.org, prabhakar.mahadev-lad.rj@bp.renesas.com, rdunlap@infradead.org, robh+dt@kernel.org, samuel@sholland.org, sunilvl@ventanamicro.com, tglx@linutronix.de, tim609@andestech.com, uwu@icenowy.me, wens@csie.org, will@kernel.org, ycliang@andestech.com Subject: Re: [PATCH v4 09/13] dt-bindings: riscv: Add T-Head PMU extension description Date: Thu, 30 Nov 2023 16:29:22 +0800 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Content-Type: text/plain; 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Thu, 30 Nov 2023 00:29:37 -0800 (PST) > >Hi Guo Ren, > >On Thu, Nov 23, 2023 at 05:14:30AM +0800, Guo Ren wrote: >> On Wed, Nov 22, 2023 at 8:17 PM Yu Chien Peter Lin >> wrote: >>> >>> Document the ISA string for T-Head performance monitor extension >>> which provides counter overflow interrupt mechanism. >>> >>> Signed-off-by: Yu Chien Peter Lin >>> --- >>> Changes v2 -> v3: >>> - New patch >>> Changes v3 -> v4: >>> - No change >>> --- >>> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ >>> 1 file changed, 6 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml >>> index c91ab0e46648..694efaea8fce 100644 >>> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml >>> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml >>> @@ -258,5 +258,11 @@ properties: >>> in commit 2e5236 ("Ztso is now ratified.") of the >>> riscv-isa-manual. >>> >>> + - const: xtheadpmu >>> + description: >>> + The T-Head performance monitor extension for counter overflow. For more >>> + details, see the chapter 12 in the Xuantie C906 user manual. >>> + https://github.com/T-head-Semi/openc906/tree/main/doc >>> + >>> additionalProperties: true >>> ... >>> -- >>> 2.34.1 >>> >> Reviewed-by: Guo Ren > >Thanks for the review. >Would you share document about T-Head PMU? > Hi, Peter Lin: You can use the following two document to get all events: https://github.com/T-head-Semi/openc906/tree/main/doc https://github.com/T-head-Semi/openc910/tree/main/doc There are also some RTL code can describe these events: https://github.com/T-head-Semi/openc910/blob/e0c4ad8ec7f8c70f649d826ebd6c949086453272/C910_RTL_FACTORY/gen_rtl/pmu/rtl/ct_hpcp_top.v#L1123 https://github.com/T-head-Semi/openc906/blob/af5614d72de7e5a4b8609c427d2e20af1deb21c4/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L543 The perf events json can also be used as document, this is already applied (with more detailed explanation): https://lore.kernel.org/all/IA1PR20MB495325FCF603BAA841E29281BBBAA@IA1PR20MB4953.namprd20.prod.outlook.com/ Best regards, Inochi