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[23.128.96.33]) by mx.google.com with ESMTPS id m8-20020a170902768800b0019c354055d0si717308pll.304.2023.11.30.00.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 00:33:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=Gv5ZR8S2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 1AB25802FA2C; Thu, 30 Nov 2023 00:33:48 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344851AbjK3Idf (ORCPT + 99 others); Thu, 30 Nov 2023 03:33:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231750AbjK3Ide (ORCPT ); Thu, 30 Nov 2023 03:33:34 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDC7D9A for ; Thu, 30 Nov 2023 00:33:40 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 63B39C433C8; Thu, 30 Nov 2023 08:33:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701333220; bh=tRGvouhLQr1KpWUDyBmlCJiZ9WRoYoSqiQEHNkqWpbM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Gv5ZR8S2wi4mCPXgnySrTlzpfn8Ix+u0SnoSorF+TU+YWGFoKQITboqfE2qa4B13k AQmoENYxBt1UZoxBdkhKodzZHHNf3IojFoFob0jYKZV5mEm++fpV7iX0CB/FUt+hR+ MwLAS+X41xv4WfWmruPOAhpu4yGZUXGzblbi2K2aNKw/GwwptHCOKlD2XF3fySsEQO BrkutL9jYwzpDJUlI2jXJaIQoa6xeg93HWgG3oo2rEHdSvzLhVH8JCTBs7gExvSYen K3Ue0JhAm73hoJuk6mDKs/FosOv1xbB95a+LvzPnHYWus6oBhUR6HIRDa/U2oTD9kL yso7IkSVapc6A== Received: from johan by xi.lan with local (Exim 4.96.2) (envelope-from ) id 1r8cUt-0006Z9-2R; Thu, 30 Nov 2023 09:34:12 +0100 Date: Thu, 30 Nov 2023 09:34:11 +0100 From: Johan Hovold To: Krzysztof Kozlowski Cc: Krishna Kurapati PSSNV , Andy Gross , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , quic_wcheng@quicinc.com, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_ppratap@quicinc.com, quic_jackp@quicinc.com Subject: Re: [PATCH 1/6] dt-bindings: usb: dwc3: Clean up hs_phy_irq in bindings Message-ID: References: <1192d91f-11bf-44af-953a-14e08e2b6ca8@quicinc.com> <004ddc69-1566-4de4-b260-0fca96a9395f@quicinc.com> <18965bb9-7afa-4892-8b71-981ba29d2cd4@quicinc.com> <6d7527bf-8c1a-49b5-a0cf-99a92098c971@quicinc.com> <85527699-f549-4728-b263-7d10c669b889@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <85527699-f549-4728-b263-7d10c669b889@linaro.org> X-Spam-Status: No, score=-1.2 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 30 Nov 2023 00:33:48 -0800 (PST) On Thu, Nov 30, 2023 at 09:16:41AM +0100, Krzysztof Kozlowski wrote: > On 29/11/2023 11:16, Johan Hovold wrote: > > On Wed, Nov 29, 2023 at 10:28:25AM +0100, Krzysztof Kozlowski wrote: > >> On 28/11/2023 12:32, Krishna Kurapati PSSNV wrote: > >>> > >>>> > >>>> So back to my initial proposal, with a slight modification moving > >>>> pwr_event first (e.g. as it is not a wakeup interrupt): > >>>> > >>>> qusb2-: > >>>> > >>>> - const: pwr_event > >>>> - const: qusb2_phy > >>>> - const: ss_phy_irq (optional) > >>>> > >>>> qusb2: > >>>> > >>>> - const: pwr_event > >>>> - const: hs_phy_irq > >>>> - const: qusb2_phy > >>>> - const: ss_phy_irq (optional) > >>>> > >>>> femto-: > >>>> - const: pwr_event > >>>> - const: dp_hs_phy_irq > >>>> - const: dm_hs_phy_irq > >>>> - const: ss_phy_irq (optional) > >>>> > >>>> femto: > >>>> - const: pwr_event > >>>> - const: hs_phy_irq > >>>> - const: dp_hs_phy_irq > >>>> - const: dm_hs_phy_irq > >>>> - const: ss_phy_irq (optional) > >> > >> I did not follow entire thread and I do not know whether you change the > >> order in existing bindings, but just in case: the entries in existing > >> bindings cannot change the order. That's a strict ABI requirement > >> recently also discussed with Bjorn, because we want to have stable DTB > >> for laptop platforms. If my comment is not relevant, then please ignore. > > > > Your comment is relevant, but I'm not sure I agree. > > > > The Qualcomm bindings are a complete mess of DT snippets copied from > > vendor trees and which have not been sanitised properly before being > > merged upstream (partly due to there not being any public documentation > > available). > > True. > > > This amounts to an unmaintainable mess which is reflected in the > > binding schemas which similarly needs to encode every random order which > > the SoC happened to use when being upstreamed. That makes the binding > > documentation unreadable too, and the next time a new SoC is upstreamed > > there is no clear hints of what the binding should look like, and we end > > up with yet another permutation. > > While in general I agree for the bindings, but here, for order of the > interrupts, I am not really sure if this contributes to unreadable or > unmaintainable binding. The more if-then clauses you have, the harder it gets for a human to make sense of the binding documents. By cleaning up the current clauses in four groups which reflect actual classes of hardware and not just arbitrary reordering and omission, it will make it much easier next time a new SoC is added. Most likely it belongs in the latest category, and a reviewer can more easily spot new mistakes if someone tries to add yet another permutation. > > As part of this exercise, we've also determined that some of the > > devicetrees that are already upstream are incorrect as well as > > incomplete. > > Sure, good explanation for an ABI break. > > > I really see no alternative to ripping of the plaster and cleaning this > > up once and for all even if it "breaks" some imaginary OS which (unlike > > Linux) relies on the current random order of these interrupts. > > > > [ If there were any real OSes actually relying on the order, then that > > would be a different thing of course. ] > > The commit breaking the ABI can justify the reasons, including expected > impact (e.g. none for Linux). > > While the second part probably you can justify (interrupts are taken by > name), the reason for ABI break like "I think it is poor code, so I will > ignore ABI" is not enough. So it's not so much about the code as the messy binding schema this results in and that that makes it harder to spot mistakes next time an SoC is upstreamed. Johan