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Message-ID: <f0844a59-7534-4195-b656-eb51586cbff6@starfivetech.com>
Date:   Thu, 30 Nov 2023 18:03:55 +0800
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Subject: Re: [PATCH v1] PCI: Add PCIE_CONFIG_REQUEST_WAIT_MS waiting time
 value
To:     Bjorn Helgaas <helgaas@kernel.org>
CC:     Bjorn Helgaas <bhelgaas@google.com>, <linux-pci@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <mason.huo@starfivetech.com>,
        <leyfoon.tan@starfivetech.com>, <minda.chen@starfivetech.com>
References: <20231129232108.GA444155@bhelgaas>
Content-Language: en-US
From:   Kevin Xie <kevin.xie@starfivetech.com>
In-Reply-To: <20231129232108.GA444155@bhelgaas>
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On 2023/11/30 7:21, Bjorn Helgaas wrote:
> On Fri, Nov 24, 2023 at 09:45:08AM +0800, Kevin Xie wrote:
>> Add the PCIE_CONFIG_REQUEST_WAIT_MS marco to define the minimum waiting
>> time between sending the first configuration request to the device and
>> exit from a conventional reset (or after link training completes).
> 
> s/marco/macro/
> 
> List the first event before the second one, i.e., the delay is from
> exit from reset to the config request.
> 

OK，I will use "from A to B" instead of "between A and B".

>> As described in the conventional reset rules of PCI specifications,
>> there are two different use cases of the value:
>> 
>>    - With a downstream port that supports link speeds <= 5.0 GT/s,
>>      the waiting is following exit from a conventional reset.
>> 
>>    - With a downstream port that supports link speeds > 5.0 GT/s,
>>      the waiting is after link training completes.
> 
> Include the spec citation here as well as in the comment below.
> 

OK, I will include the spec citation here.

> I assume there are follow-on patches that actually use this?  Can we
> make this the first patch in a series so we know we don't have an
> unused macro lying around?
> 

Yes, we will use the marco in the next version of our PCIe controller patches.
Here is the link of current version patch series:
https://lore.kernel.org/lkml/20231115114912.71448-20-minda.chen@starfivetech.com/T/#u 

Do you mean that I should put this patch back to the above series as one of the separate patches?

Thanks for your review.

>> Signed-off-by: Kevin Xie <kevin.xie@starfivetech.com>
>> Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
>> ---
>>  drivers/pci/pci.h | 7 +++++++
>>  1 file changed, 7 insertions(+)
>> 
>> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
>> index 5ecbcf041179..4ca8766e546e 100644
>> --- a/drivers/pci/pci.h
>> +++ b/drivers/pci/pci.h
>> @@ -22,6 +22,13 @@
>>   */
>>  #define PCIE_PME_TO_L2_TIMEOUT_US	10000
>>  
>> +/*
>> + * PCIe r6.0, sec 6.6.1, <Conventional Reset>
>> + * Requires a minimum waiting of 100ms before sending a configuration
>> + * request to the device.
>> + */
>> +#define PCIE_CONFIG_REQUEST_WAIT_MS	100
>> +
>>  extern const unsigned char pcie_link_speed[];
>>  extern bool pci_early_dump;
>>  
>> -- 
>> 2.25.1
>>