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Message-ID: <081b3aab0c9350a42fdb69149b563c7aef4af0d5.camel@redhat.com>
Subject: Re: [PATCH v3] net: stmmac: fix FPE events losing
From:   Paolo Abeni <pabeni@redhat.com>
To:     Serge Semin <fancer.lancer@gmail.com>
Cc:     Jianheng Zhang <Jianheng.Zhang@synopsys.com>,
        Alexandre Torgue <alexandre.torgue@foss.st.com>,
        Jose Abreu <Jose.Abreu@synopsys.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Maxime Coquelin <mcoquelin.stm32@gmail.com>,
        Simon Horman <horms@kernel.org>,
        Andrew Halaney <ahalaney@redhat.com>,
        Bartosz Golaszewski <bartosz.golaszewski@linaro.org>,
        Shenwei Wang <shenwei.wang@nxp.com>,
        Johannes Zink <j.zink@pengutronix.de>,
        "Russell King (Oracle" <rmk+kernel@armlinux.org.uk>,
        Jochen Henneberg <jh@henneberg-systemdesign.com>,
        Voon Weifeng <weifeng.voon@intel.com>,
        Mohammad Athari Bin Ismail <mohammad.athari.ismail@intel.com>,
        Ong Boon Leong <boon.leong.ong@intel.com>,
        Tan Tee Min <tee.min.tan@intel.com>,
        "open list:STMMAC ETHERNET DRIVER" <netdev@vger.kernel.org>,
        "moderated list:ARM/STM32 ARCHITECTURE" 
        <linux-stm32@st-md-mailman.stormreply.com>,
        "moderated list:ARM/STM32 ARCHITECTURE" 
        <linux-arm-kernel@lists.infradead.org>,
        open list <linux-kernel@vger.kernel.org>,
        James Li <James.Li1@synopsys.com>,
        Martin McKenny <Martin.McKenny@synopsys.com>
Date:   Thu, 30 Nov 2023 15:09:36 +0100
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On Thu, 2023-11-30 at 16:09 +0300, Serge Semin wrote:
> Hi Paolo
>=20
> On Thu, Nov 30, 2023 at 10:55:34AM +0100, Paolo Abeni wrote:
> > On Tue, 2023-11-28 at 05:56 +0000, Jianheng Zhang wrote:
> > > The status bits of register MAC_FPE_CTRL_STS are clear on read. Using
> > > 32-bit read for MAC_FPE_CTRL_STS in dwmac5_fpe_configure() and
> > > dwmac5_fpe_send_mpacket() clear the status bits. Then the stmmac inte=
rrupt
> > > handler missing FPE event status and leads to FPE handshaking failure=
 and
> > > retries.
> > > To avoid clear status bits of MAC_FPE_CTRL_STS in dwmac5_fpe_configur=
e()
> > > and dwmac5_fpe_send_mpacket(), add fpe_csr to stmmac_fpe_cfg structur=
e to
> > > cache the control bits of MAC_FPE_CTRL_STS and to avoid reading
> > > MAC_FPE_CTRL_STS in those methods.
> > >=20
> > > Fixes: 5a5586112b92 ("net: stmmac: support FPE link partner hand-shak=
ing procedure")
> > > Reviewed-by: Serge Semin <fancer.lancer@gmail.com>
> > > Signed-off-by: Jianheng Zhang <jianheng@synopsys.com>
> > > ---
> > >  drivers/net/ethernet/stmicro/stmmac/dwmac5.c       | 45 +++++++++---=
----------
> > >  drivers/net/ethernet/stmicro/stmmac/dwmac5.h       |  4 +-
> > >  .../net/ethernet/stmicro/stmmac/dwxgmac2_core.c    |  3 +-
> > >  drivers/net/ethernet/stmicro/stmmac/hwif.h         |  4 +-
> > >  drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |  8 +++-
> > >  drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c    |  1 +
> > >  include/linux/stmmac.h                             |  1 +
> > >  7 files changed, 36 insertions(+), 30 deletions(-)
> > >=20
> > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c b/drivers/n=
et/ethernet/stmicro/stmmac/dwmac5.c
> > > index e95d35f..8fd1675 100644
> > > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac5.c
> > > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac5.c
> > > @@ -710,28 +710,22 @@ void dwmac5_est_irq_status(void __iomem *ioaddr=
, struct net_device *dev,
> > >  	}
> > >  }
> > > =20
> > > -void dwmac5_fpe_configure(void __iomem *ioaddr, u32 num_txq, u32 num=
_rxq,
> > > +void dwmac5_fpe_configure(void __iomem *ioaddr, struct stmmac_fpe_cf=
g *cfg,
> > > +			  u32 num_txq, u32 num_rxq,
> > >  			  bool enable)
> > >  {
> > >  	u32 value;
> > > =20
> > > -	if (!enable) {
> > > -		value =3D readl(ioaddr + MAC_FPE_CTRL_STS);
> > > -
> > > -		value &=3D ~EFPE;
> > > -
> > > -		writel(value, ioaddr + MAC_FPE_CTRL_STS);
> > > -		return;
> > > +	if (enable) {
> > > +		cfg->fpe_csr =3D EFPE;
> > > +		value =3D readl(ioaddr + GMAC_RXQ_CTRL1);
> > > +		value &=3D ~GMAC_RXQCTRL_FPRQ;
> > > +		value |=3D (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
> > > +		writel(value, ioaddr + GMAC_RXQ_CTRL1);
> > > +	} else {
> > > +		cfg->fpe_csr =3D 0;
> > >  	}
> > > -
> > > -	value =3D readl(ioaddr + GMAC_RXQ_CTRL1);
> > > -	value &=3D ~GMAC_RXQCTRL_FPRQ;
> > > -	value |=3D (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
> > > -	writel(value, ioaddr + GMAC_RXQ_CTRL1);
> > > -
> > > -	value =3D readl(ioaddr + MAC_FPE_CTRL_STS);
> > > -	value |=3D EFPE;
> > > -	writel(value, ioaddr + MAC_FPE_CTRL_STS);
> > > +	writel(cfg->fpe_csr, ioaddr + MAC_FPE_CTRL_STS);
> > >  }
> > > =20
> > >  int dwmac5_fpe_irq_status(void __iomem *ioaddr, struct net_device *d=
ev)
> > > @@ -741,6 +735,9 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr, s=
truct net_device *dev)
> > > =20
> > >  	status =3D FPE_EVENT_UNKNOWN;
> > > =20
> > > +	/* Reads from the MAC_FPE_CTRL_STS register should only be performe=
d
> > > +	 * here, since the status flags of MAC_FPE_CTRL_STS are "clear on r=
ead"
> > > +	 */
> > >  	value =3D readl(ioaddr + MAC_FPE_CTRL_STS);
> > > =20
> > >  	if (value & TRSP) {
> > > @@ -766,19 +763,15 @@ int dwmac5_fpe_irq_status(void __iomem *ioaddr,=
 struct net_device *dev)
> > >  	return status;
> > >  }
> > > =20
> > > -void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, enum stmmac_mpack=
et_type type)
> > > +void dwmac5_fpe_send_mpacket(void __iomem *ioaddr, struct stmmac_fpe=
_cfg *cfg,
> > > +			     enum stmmac_mpacket_type type)
> > >  {
> > > -	u32 value;
> > > +	u32 value =3D cfg->fpe_csr;
> > > =20
> > > -	value =3D readl(ioaddr + MAC_FPE_CTRL_STS);
> > > -
> > > -	if (type =3D=3D MPACKET_VERIFY) {
> > > -		value &=3D ~SRSP;
> > > +	if (type =3D=3D MPACKET_VERIFY)
> > >  		value |=3D SVER;
> > > -	} else {
> > > -		value &=3D ~SVER;
> > > +	else if (type =3D=3D MPACKET_RESPONSE)
> > >  		value |=3D SRSP;
> > > -	}
> > > =20
> > >  	writel(value, ioaddr + MAC_FPE_CTRL_STS);
> > >  }
> >=20
>=20
> > It's unclear to me why it's not necessary to preserve the SVER/SRSP
> > bits across MAC_FPE_CTRL_STS writes. I guess they are not part of the
> > status bits? perhaps an explicit comment somewhere will help?
>=20
> The SRSP and SVER are self-cleared flags with no effect on zero
> writing. Their responsibility is to emit the Respond and Verify
> mPackets respectively. As soon as the packets are sent, the flags will
> be reset by hardware automatically. So no, they aren't a part of the
> status bits.
>=20
> Note since 'value' now isn't read from the MAC_FPE_CTRL_STS register,
> there is no point in clearing up these flags in the local variable
> because 'value' has now them cleared by default.
>=20
> Not sure whether a comment about that is required, since the described
> behavior is well documented in the Synopsys HW-manual.

Thanks for the explanation, it clarifies the things to me. I agree
there is no need for a patch change.

Cheers,

Paolo