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Date:   Thu, 30 Nov 2023 14:12:22 +0000
From:   Conor Dooley <conor@kernel.org>
To:     Emil Renner Berthing <emil.renner.berthing@canonical.com>
Cc:     linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Subject: Re: [PATCH v1 0/8] Add JH7100 errata and update device tree
Message-ID: <20231130-skating-shindig-af43058fc8ff@spud>
References: <20231126232746.264302-1-emil.renner.berthing@canonical.com>
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On Mon, Nov 27, 2023 at 12:27:38AM +0100, Emil Renner Berthing wrote:
> Now that the driver for the SiFive cache controller supports manual
> flushing as non-standard cache operations[1] we can add an errata option
> for the StarFive JH7100 SoC and update the device tree with the cache
> controller, dedicated DMA pool and add MMC nodes for the SD-card and
> wifi.
>=20
> This series needs the following commit in [1] to work properly:
>=20
> 0d5701dc9cd6 ("soc: sifive: ccache: Add StarFive JH7100 support")
>=20
> [1]: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/log/=
?h=3Driscv-soc-for-next

This stuff all seems fine to me. I'd like Palmer to take the first
patch, or I suppose I could take it alongside the cache driver changes
with an Ack.

Cheers,
Conor.

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