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[34.150.132.193]) by smtp.gmail.com with ESMTPSA id b18-20020a0c9b12000000b0065b13180892sm641645qve.16.2023.11.30.08.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 08:25:01 -0800 (PST) Date: Thu, 30 Nov 2023 16:24:59 +0000 From: Paz Zcharya To: Andrzej Hajda Cc: Subrata Banik , Tvrtko Ursulin , intel-gfx@lists.freedesktop.org, Marcin Wojtas , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Sean Paul , matthew.auld@intel.com, Daniel Vetter , Rodrigo Vivi , Drew Davenport , David Airlie , Nirmoy Das Subject: Re: [Intel-gfx] [PATCH] drm/i915/display: Fix phys_base to be relative not absolute Message-ID: References: <20231105172718.18673-1-pazz@chromium.org> <8dd6f4da-dcc9-4ea3-8395-bf048b0dbc93@intel.com> <6f08cfee-a60b-4f6e-b69a-20517c563259@intel.com> <51baffb9-2249-4080-a245-eb1e03c02b9b@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <51baffb9-2249-4080-a245-eb1e03c02b9b@intel.com> X-Spam-Status: No, score=0.4 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FSL_HELO_FAKE,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Thu, 30 Nov 2023 08:25:14 -0800 (PST) On Tue, Nov 28, 2023 at 12:12:08PM +0100, Andrzej Hajda wrote: > On 28.11.2023 04:47, Paz Zcharya wrote: > > > > On Mon, Nov 27, 2023 at 8:20 PM Paz Zcharya wrote: > > > > > > On 21.11.2023 13:06, Andrzej Hajda wrote: > > > > > > > The simplest approach would be then do the same as in case of DGFX: > > > > gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm; > > > > gen8_pte_t pte; > > > > > > > > gte += base / I915_GTT_PAGE_SIZE; > > > > > > > > pte = ioread64(gte); > > > > phys_base = pte & I915_GTT_PAGE_MASK; > > > > > > > > Regards > > > > Andrzej > > > > Hey Andrzej, > > > > On a second thought, what do you think about something like > > > > + gen8_pte_t __iomem *gte = to_gt(i915)->ggtt->gsm; > > + gen8_pte_t pte; > > + gte += base / I915_GTT_PAGE_SIZE; > > + pte = ioread64(gte); > > + pte = pte & I915_GTT_PAGE_MASK; > > + phys_base = pte - i915->mm.stolen_region->region.start; > > > > The only difference is the last line. > > Bingo :) It seems to be generic algorithm to get phys_base for all > platforms: > - on older platforms stolen_region points to system memory which starts at > 0, > - on DG2 it uses lmem region which starts at 0 as well, > - on MTL stolen_region points to stolen-local which starts at 0x800000. > > So this whole "if (IS_DGFX(i915)) {...} else {...}" could be replaced > with sth generic. > 1. Find pte. > 2. if(IS_DGFX(i915) && pte & GEN12_GGTT_PTE_LM) mem = > i915->mm.regions[INTEL_REGION_LMEM_0] else mem = i915->mm.stolen_region > 3. phys_base = (pte & I915_GTT_PAGE_MASK) - mem->region.start; > > Regards > Andrzej > > Hey Andrzej, I uploaded https://patchwork.freedesktop.org/series/127130/ based on algorithm. Please take a look and let me know if you'd like me to change anything. Really appreciate all of your help! Best, Paz