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References: <20231129152230.7931-1-n.zhandarovich@fintech.ru>
In-Reply-To: <20231129152230.7931-1-n.zhandarovich@fintech.ru>
From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Thu, 30 Nov 2023 12:06:19 -0500
Message-ID: <CADnq5_O+O-395Brq+OHR3YEDaeTwQsMseJynv4Mm3L-KotO-5g@mail.gmail.com>
Subject: Re: [PATCH] drm/radeon/r600_cs: Fix possible int overflows in r600_cs_check_reg()
To:     Nikita Zhandarovich <n.zhandarovich@fintech.ru>
Cc:     Alex Deucher <alexander.deucher@amd.com>,
        =?UTF-8?Q?Christian_K=C3=B6nig?= <christian.koenig@amd.com>,
        "Pan, Xinhui" <Xinhui.Pan@amd.com>, linux-kernel@vger.kernel.org,
        amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
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Applied.  Thanks!

On Wed, Nov 29, 2023 at 10:28=E2=80=AFAM Nikita Zhandarovich
<n.zhandarovich@fintech.ru> wrote:
>
> While improbable, there may be a chance of hitting integer
> overflow when the result of radeon_get_ib_value() gets shifted
> left.
>
> Avoid it by casting one of the operands to larger data type (u64).
>
> Found by Linux Verification Center (linuxtesting.org) with static
> analysis tool SVACE.
>
> Fixes: 1729dd33d20b ("drm/radeon/kms: r600 CS parser fixes")
> Signed-off-by: Nikita Zhandarovich <n.zhandarovich@fintech.ru>
> ---
>  drivers/gpu/drm/radeon/r600_cs.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r6=
00_cs.c
> index 638f861af80f..6cf54a747749 100644
> --- a/drivers/gpu/drm/radeon/r600_cs.c
> +++ b/drivers/gpu/drm/radeon/r600_cs.c
> @@ -1275,7 +1275,7 @@ static int r600_cs_check_reg(struct radeon_cs_parse=
r *p, u32 reg, u32 idx)
>                         return -EINVAL;
>                 }
>                 tmp =3D (reg - CB_COLOR0_BASE) / 4;
> -               track->cb_color_bo_offset[tmp] =3D radeon_get_ib_value(p,=
 idx) << 8;
> +               track->cb_color_bo_offset[tmp] =3D (u64)radeon_get_ib_val=
ue(p, idx) << 8;
>                 ib[idx] +=3D (u32)((reloc->gpu_offset >> 8) & 0xffffffff)=
;
>                 track->cb_color_base_last[tmp] =3D ib[idx];
>                 track->cb_color_bo[tmp] =3D reloc->robj;
> @@ -1302,7 +1302,7 @@ static int r600_cs_check_reg(struct radeon_cs_parse=
r *p, u32 reg, u32 idx)
>                                         "0x%04X\n", reg);
>                         return -EINVAL;
>                 }
> -               track->htile_offset =3D radeon_get_ib_value(p, idx) << 8;
> +               track->htile_offset =3D (u64)radeon_get_ib_value(p, idx) =
<< 8;
>                 ib[idx] +=3D (u32)((reloc->gpu_offset >> 8) & 0xffffffff)=
;
>                 track->htile_bo =3D reloc->robj;
>                 track->db_dirty =3D true;
> --
> 2.25.1
>