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[2620:137:e000::3:8]) by mx.google.com with ESMTPS id v17-20020a056a00149100b006cd9e5b2d84si2780178pfu.328.2023.11.30.21.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 21:45:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=DvBFTnzn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id D24CF80FC1AF; Thu, 30 Nov 2023 21:44:57 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1377541AbjLAFoW (ORCPT + 99 others); Fri, 1 Dec 2023 00:44:22 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1377474AbjLAFoT (ORCPT ); Fri, 1 Dec 2023 00:44:19 -0500 Received: from mail-ot1-x32a.google.com (mail-ot1-x32a.google.com [IPv6:2607:f8b0:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 81BD91724 for ; Thu, 30 Nov 2023 21:44:24 -0800 (PST) Received: by mail-ot1-x32a.google.com with SMTP id 46e09a7af769-6d7e8da5e99so102634a34.2 for ; Thu, 30 Nov 2023 21:44:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1701409464; x=1702014264; darn=vger.kernel.org; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=1S566PVY0OEY56vpzJTLANuberH+LTJgX6nfbZ1a8fs=; b=DvBFTnznQGuaZnGNEYhSFUvCq8A1T4EvIWSXTt8NRq1b7YUIxmWZfBTFlLPAdWVH0A BvrG5sJ6M/QyLbJY3w676u9fAMQB1akycxbGe/LNE0kLFCyhlJSOtbEkmDN2iH+5GhBT PM+HA+lDU7RTKAqkeQDNjv7pCjUPgn+IoMvEkdIPZaLu49DQUM7XNCZSRSDuwzMqKpY7 v9oPNYh/tO7H1Bg4q5O/5MADSvDkiTLoBaeoby87ks2hYaY/B275PmjUm82/BddfDnuU YSMebrafvDaoAAfYn+kcs9B7a3W/KE3OJ1ln8Qg39vlPFsFy2giCe+ecjL6pUabQ81NH kJ/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701409464; x=1702014264; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=1S566PVY0OEY56vpzJTLANuberH+LTJgX6nfbZ1a8fs=; b=CB4A264zJgFcKUkol7K/vRAypT0UJzvbGOKNHWG78dOBhtG36MczJj/zjSo14luZ6g Lw8MePLJSsgiqRk45l5kKrYD+UolmVh+IsiT6qdfCW6cSeUIOHFNLPPCLXQ1UPy/J24k ryACPbpHbCF8zsZPowwfug6k7Ia0uGaDXUq9bVYx/PNDAqXBt8X3pbgH13WTQJhJXQn4 whiAOTseZSJIJLuA26wyyaJYDx3FMPiOntJqaib4YuoijKcOV9eoKt0sEhSOEM4cXKo8 nl/5y6DJ5Ye64EzXLPVlLgGYd5ex+GYHdoA0PseQun25+zkwvbITRcqF6UQiY5fzVBaG nqrg== X-Gm-Message-State: AOJu0YykI7fCsoWrCGF12jR8oWu9lXYdIKrbiBlXnC3aPBY2TQujFWc3 YHAlSKzVCiiJsS0C1lEQcI6uIkPqM2JpnG8zbggPdg== X-Received: by 2002:a05:6871:8903:b0:1fa:ecf1:8b67 with SMTP id ti3-20020a056871890300b001faecf18b67mr882373oab.59.1701409463729; Thu, 30 Nov 2023 21:44:23 -0800 (PST) Received: from ghost ([2601:647:5700:6860:9075:c975:12d3:f5fb]) by smtp.gmail.com with ESMTPSA id l20-20020a9d6a94000000b006d81fbeede9sm397380otq.27.2023.11.30.21.44.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Nov 2023 21:44:23 -0800 (PST) Date: Thu, 30 Nov 2023 21:44:20 -0800 From: Charlie Jenkins To: Xiao Wang Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, arnd@arndb.de, geert@linux-m68k.org, haicheng.li@intel.com, linux-arch@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] riscv: Avoid code duplication with generic bitops implementation Message-ID: References: <20231112094421.4014931-1-xiao.w.wang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231112094421.4014931-1-xiao.w.wang@intel.com> X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Thu, 30 Nov 2023 21:44:58 -0800 (PST) On Sun, Nov 12, 2023 at 05:44:21PM +0800, Xiao Wang wrote: > There's code duplication between the fallback implementation for bitops > __ffs/__fls/ffs/fls API and the generic C implementation in > include/asm-generic/bitops/. To avoid this duplication, this patch renames > the generic C implementation by adding a "generic_" prefix to them, then we > can use these generic APIs as fallback. > > Suggested-by: Geert Uytterhoeven > Signed-off-by: Xiao Wang > --- > arch/riscv/include/asm/bitops.h | 138 +++++------------------------ > include/asm-generic/bitops/__ffs.h | 8 +- > include/asm-generic/bitops/__fls.h | 8 +- > include/asm-generic/bitops/ffs.h | 8 +- > include/asm-generic/bitops/fls.h | 8 +- > 5 files changed, 48 insertions(+), 122 deletions(-) > > diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h > index f7c167646460..23f7c122b151 100644 > --- a/arch/riscv/include/asm/bitops.h > +++ b/arch/riscv/include/asm/bitops.h > @@ -22,6 +22,16 @@ > #include > > #else > +#define __HAVE_ARCH___FFS > +#define __HAVE_ARCH___FLS > +#define __HAVE_ARCH_FFS > +#define __HAVE_ARCH_FLS > + > +#include > +#include > +#include > +#include > + > #include > #include > > @@ -37,8 +47,6 @@ > > static __always_inline unsigned long variable__ffs(unsigned long word) > { > - int num; > - > asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0, > RISCV_ISA_EXT_ZBB, 1) > : : : : legacy); > @@ -52,32 +60,7 @@ static __always_inline unsigned long variable__ffs(unsigned long word) > return word; > > legacy: > - num = 0; > -#if BITS_PER_LONG == 64 > - if ((word & 0xffffffff) == 0) { > - num += 32; > - word >>= 32; > - } > -#endif > - if ((word & 0xffff) == 0) { > - num += 16; > - word >>= 16; > - } > - if ((word & 0xff) == 0) { > - num += 8; > - word >>= 8; > - } > - if ((word & 0xf) == 0) { > - num += 4; > - word >>= 4; > - } > - if ((word & 0x3) == 0) { > - num += 2; > - word >>= 2; > - } > - if ((word & 0x1) == 0) > - num += 1; > - return num; > + return generic___ffs(word); > } > > /** > @@ -93,8 +76,6 @@ static __always_inline unsigned long variable__ffs(unsigned long word) > > static __always_inline unsigned long variable__fls(unsigned long word) > { > - int num; > - > asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0, > RISCV_ISA_EXT_ZBB, 1) > : : : : legacy); > @@ -108,32 +89,7 @@ static __always_inline unsigned long variable__fls(unsigned long word) > return BITS_PER_LONG - 1 - word; > > legacy: > - num = BITS_PER_LONG - 1; > -#if BITS_PER_LONG == 64 > - if (!(word & (~0ul << 32))) { > - num -= 32; > - word <<= 32; > - } > -#endif > - if (!(word & (~0ul << (BITS_PER_LONG - 16)))) { > - num -= 16; > - word <<= 16; > - } > - if (!(word & (~0ul << (BITS_PER_LONG - 8)))) { > - num -= 8; > - word <<= 8; > - } > - if (!(word & (~0ul << (BITS_PER_LONG - 4)))) { > - num -= 4; > - word <<= 4; > - } > - if (!(word & (~0ul << (BITS_PER_LONG - 2)))) { > - num -= 2; > - word <<= 2; > - } > - if (!(word & (~0ul << (BITS_PER_LONG - 1)))) > - num -= 1; > - return num; > + return generic___fls(word); > } > > /** > @@ -149,46 +105,23 @@ static __always_inline unsigned long variable__fls(unsigned long word) > > static __always_inline int variable_ffs(int x) > { > - int r; > - > - if (!x) > - return 0; > - > asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0, > RISCV_ISA_EXT_ZBB, 1) > : : : : legacy); > > + if (!x) > + return 0; > + > asm volatile (".option push\n" > ".option arch,+zbb\n" > CTZW "%0, %1\n" > ".option pop\n" > - : "=r" (r) : "r" (x) :); > + : "=r" (x) : "r" (x) :); > > - return r + 1; > + return x + 1; > > legacy: > - r = 1; > - if (!(x & 0xffff)) { > - x >>= 16; > - r += 16; > - } > - if (!(x & 0xff)) { > - x >>= 8; > - r += 8; > - } > - if (!(x & 0xf)) { > - x >>= 4; > - r += 4; > - } > - if (!(x & 3)) { > - x >>= 2; > - r += 2; > - } > - if (!(x & 1)) { > - x >>= 1; > - r += 1; > - } > - return r; > + return generic_ffs(x); > } > > /** > @@ -204,46 +137,23 @@ static __always_inline int variable_ffs(int x) > > static __always_inline int variable_fls(unsigned int x) > { > - int r; > - > - if (!x) > - return 0; > - > asm_volatile_goto(ALTERNATIVE("j %l[legacy]", "nop", 0, > RISCV_ISA_EXT_ZBB, 1) > : : : : legacy); > > + if (!x) > + return 0; > + > asm volatile (".option push\n" > ".option arch,+zbb\n" > CLZW "%0, %1\n" > ".option pop\n" > - : "=r" (r) : "r" (x) :); > + : "=r" (x) : "r" (x) :); > > - return 32 - r; > + return 32 - x; > > legacy: > - r = 32; > - if (!(x & 0xffff0000u)) { > - x <<= 16; > - r -= 16; > - } > - if (!(x & 0xff000000u)) { > - x <<= 8; > - r -= 8; > - } > - if (!(x & 0xf0000000u)) { > - x <<= 4; > - r -= 4; > - } > - if (!(x & 0xc0000000u)) { > - x <<= 2; > - r -= 2; > - } > - if (!(x & 0x80000000u)) { > - x <<= 1; > - r -= 1; > - } > - return r; > + return generic_fls(x); > } > > /** > diff --git a/include/asm-generic/bitops/__ffs.h b/include/asm-generic/bitops/__ffs.h > index 39e56e1c7203..446fea6dda78 100644 > --- a/include/asm-generic/bitops/__ffs.h > +++ b/include/asm-generic/bitops/__ffs.h > @@ -5,12 +5,12 @@ > #include > > /** > - * __ffs - find first bit in word. > + * generic___ffs - find first bit in word. > * @word: The word to search > * > * Undefined if no bit exists, so code should check against 0 first. > */ > -static __always_inline unsigned long __ffs(unsigned long word) > +static __always_inline unsigned long generic___ffs(unsigned long word) > { > int num = 0; > > @@ -41,4 +41,8 @@ static __always_inline unsigned long __ffs(unsigned long word) > return num; > } > > +#ifndef __HAVE_ARCH___FFS > +#define __ffs(word) generic___ffs(word) > +#endif > + > #endif /* _ASM_GENERIC_BITOPS___FFS_H_ */ > diff --git a/include/asm-generic/bitops/__fls.h b/include/asm-generic/bitops/__fls.h > index 03f721a8a2b1..54ccccf96e21 100644 > --- a/include/asm-generic/bitops/__fls.h > +++ b/include/asm-generic/bitops/__fls.h > @@ -5,12 +5,12 @@ > #include > > /** > - * __fls - find last (most-significant) set bit in a long word > + * generic___fls - find last (most-significant) set bit in a long word > * @word: the word to search > * > * Undefined if no set bit exists, so code should check against 0 first. > */ > -static __always_inline unsigned long __fls(unsigned long word) > +static __always_inline unsigned long generic___fls(unsigned long word) > { > int num = BITS_PER_LONG - 1; > > @@ -41,4 +41,8 @@ static __always_inline unsigned long __fls(unsigned long word) > return num; > } > > +#ifndef __HAVE_ARCH___FLS > +#define __fls(word) generic___fls(word) > +#endif > + > #endif /* _ASM_GENERIC_BITOPS___FLS_H_ */ > diff --git a/include/asm-generic/bitops/ffs.h b/include/asm-generic/bitops/ffs.h > index 323fd5d6ae26..4c43f242daeb 100644 > --- a/include/asm-generic/bitops/ffs.h > +++ b/include/asm-generic/bitops/ffs.h > @@ -3,14 +3,14 @@ > #define _ASM_GENERIC_BITOPS_FFS_H_ > > /** > - * ffs - find first bit set > + * generic_ffs - find first bit set > * @x: the word to search > * > * This is defined the same way as > * the libc and compiler builtin ffs routines, therefore > * differs in spirit from ffz (man ffs). > */ > -static inline int ffs(int x) > +static inline int generic_ffs(int x) > { > int r = 1; > > @@ -39,4 +39,8 @@ static inline int ffs(int x) > return r; > } > > +#ifndef __HAVE_ARCH_FFS > +#define ffs(x) generic_ffs(x) > +#endif > + > #endif /* _ASM_GENERIC_BITOPS_FFS_H_ */ > diff --git a/include/asm-generic/bitops/fls.h b/include/asm-generic/bitops/fls.h > index b168bb10e1be..26f3ce1dd6e4 100644 > --- a/include/asm-generic/bitops/fls.h > +++ b/include/asm-generic/bitops/fls.h > @@ -3,14 +3,14 @@ > #define _ASM_GENERIC_BITOPS_FLS_H_ > > /** > - * fls - find last (most-significant) bit set > + * generic_fls - find last (most-significant) bit set > * @x: the word to search > * > * This is defined the same way as ffs. > * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. > */ > > -static __always_inline int fls(unsigned int x) > +static __always_inline int generic_fls(unsigned int x) > { > int r = 32; > > @@ -39,4 +39,8 @@ static __always_inline int fls(unsigned int x) > return r; > } > > +#ifndef __HAVE_ARCH_FLS > +#define fls(x) generic_fls(x) > +#endif > + > #endif /* _ASM_GENERIC_BITOPS_FLS_H_ */ > -- > 2.25.1 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Apologies I missed this, looks great. Reviewed-by: Charlie Jenkins