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[2620:137:e000::3:4]) by mx.google.com with ESMTPS id ik26-20020a170902ab1a00b001c9b15bf936si958717plb.220.2023.12.01.06.25.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Dec 2023 06:25:37 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=sntech.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 788E384C29B0; Fri, 1 Dec 2023 06:25:25 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379161AbjLAOZF (ORCPT + 99 others); Fri, 1 Dec 2023 09:25:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379143AbjLAOZD (ORCPT ); Fri, 1 Dec 2023 09:25:03 -0500 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 911E610F4; Fri, 1 Dec 2023 06:25:08 -0800 (PST) Received: from i53875b61.versanet.de ([83.135.91.97] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1r94Rs-0000PA-CQ; Fri, 01 Dec 2023 15:24:56 +0100 From: Heiko Stuebner To: andrew@lunn.ch, hkallweit1@gmail.com Cc: linux@armlinux.org.uk, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, quentin.schulz@theobroma-systems.com, heiko@sntech.de, Heiko Stuebner Subject: [PATCH] net: mdio: enable optional clock when registering a phy from devicetree Date: Fri, 1 Dec 2023 15:24:53 +0100 Message-Id: <20231201142453.324697-1-heiko@sntech.de> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Fri, 01 Dec 2023 06:25:25 -0800 (PST) From: Heiko Stuebner The ethernet-phy binding (now) specifys that phys can declare a clock supply. Phy driver itself will handle this when probing the phy-driver. But there is a gap when trying to detect phys, because the mdio-bus needs to talk to the phy to get its phy-id. Using actual phy-ids in the dt like compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; of course circumvents this, but in turn hard-codes the phy. With boards often having multiple phy options and the mdio-bus being able to actually probe devices, this feels like a step back. So check for the existence of a phy-clock per the -dtbinding in the of_mdiobus_register_phy() and enable the clock around the fwnode_mdiobus_register_phy() call which tries to determine the phy-id. Signed-off-by: Heiko Stuebner --- drivers/net/mdio/of_mdio.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/net/mdio/of_mdio.c b/drivers/net/mdio/of_mdio.c index 64ebcb6d235c..895b12849b23 100644 --- a/drivers/net/mdio/of_mdio.c +++ b/drivers/net/mdio/of_mdio.c @@ -8,6 +8,7 @@ * out of the OpenFirmware device tree and using it to populate an mii_bus. */ +#include #include #include #include @@ -15,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -46,7 +48,37 @@ EXPORT_SYMBOL(of_mdiobus_phy_device_register); static int of_mdiobus_register_phy(struct mii_bus *mdio, struct device_node *child, u32 addr) { - return fwnode_mdiobus_register_phy(mdio, of_fwnode_handle(child), addr); + struct clk *clk = NULL; + int ret; + + /* ethernet-phy binding specifies a maximum of 1 clock */ + if (of_clk_get_parent_count(child) == 1) { + clk = of_clk_get(child, 0); + if (IS_ERR(clk)) { + if (PTR_ERR(clk) != -ENOENT) + return dev_err_probe(&mdio->dev, PTR_ERR(clk), + "Could not get defined clock for MDIO device at address %u\n", + addr); + + clk = NULL; + } + } + + ret = clk_prepare_enable(clk); + if (ret < 0) { + clk_put(clk); + dev_err(&mdio->dev, + "Could not enable clock for MDIO device at address %u: %d\n", + addr, ret); + return ret; + } + + ret = fwnode_mdiobus_register_phy(mdio, of_fwnode_handle(child), addr); + + clk_disable_unprepare(clk); + clk_put(clk); + + return ret; } static int of_mdiobus_register_device(struct mii_bus *mdio, -- 2.39.2