Received: by 2002:a05:7412:b10a:b0:f3:1519:9f41 with SMTP id az10csp1090667rdb; Fri, 1 Dec 2023 06:56:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IGQ1mE/Jf5ZmngwIqQXHMj5Fllrf88aiI+JU5kFw/KKVZFlDUwG9h1CAtMMCPM2EhpeeXg1 X-Received: by 2002:a05:6a21:99a7:b0:18b:208b:7043 with SMTP id ve39-20020a056a2199a700b0018b208b7043mr34535121pzb.49.1701442593957; Fri, 01 Dec 2023 06:56:33 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1701442593; cv=none; d=google.com; s=arc-20160816; b=vpWuzpmGgMZWDByP+TvuI0tAftU39asdNSvCm7AfosmkMrcQSa7aigCT744EVG/EKD eIDwRdT4jI0nqBvTZRtxuQZEcwWrMPfahJ5wpVfj5hkp4yPwZtW4c3fkszohUdXII/Kf os7X41Kq8ft1llX6v8RMFCDcCfOUhDMz3uB11puw02Abmf1dyxEDQRfgy05ydRhq8FCJ Phrh5DRcenkAX6nMxVQlUJeIyVNcjiuSx/u54nI8dpFAW7oMNcDxmahvdYlaeMsdEXpg I+RKUd05vBGkV8f+23Yf7JmvvLlmtUfWV7CpZWGTK1OfCL0ktANMOCQOySMKJ2a1snIn BwPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=4GUnoQB6C0nbSWJDIlHr81/MM7PllZzxNFJ+5yHtJSw=; fh=JsBKXa2RgEU3LR581ROC7VboCe7J98nT9yys/5cx2Wk=; b=Z5HA+gQSryp9K1x+gc0Z3Z4shYiGw6Oj8msT/B0jvATfEE52HCt46D5MqCPeKjHJId MuTJIn8j2qy+CrrG8QdBNd7uoyEFkr2PlyXUPZj/vTgQeM7FOdwNdLRSsCjWSYuyF6yJ EW9mJU+smZRoeOiS8pbpcWemFdB03BlfQHoDznQ3APyRtpT/sbtngz9AynpO4vnzMmDZ +BF8Ck4eyWJYLGeeNmYTRZbLwJx2XOx3XEvPW2MRq8ac91qzwumaAmTYvzybwgRX2utq kBMhd+KTM5LBDseP6VUAJZdoQSfmrkEChXI53YJLWE/PM7tKS4UZ9xToY50znRENN83l eilg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id u3-20020a63df03000000b005b90e67f438si3379671pgg.106.2023.12.01.06.56.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Dec 2023 06:56:33 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 1589883741D0; Fri, 1 Dec 2023 06:56:09 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1379266AbjLAOzy (ORCPT + 99 others); Fri, 1 Dec 2023 09:55:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1379252AbjLAOzw (ORCPT ); Fri, 1 Dec 2023 09:55:52 -0500 Received: from mail11.truemail.it (mail11.truemail.it [217.194.8.81]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85B7B103; Fri, 1 Dec 2023 06:55:57 -0800 (PST) Received: from francesco-nb.pivistrello.it (93-49-2-63.ip317.fastwebnet.it [93.49.2.63]) by mail11.truemail.it (Postfix) with ESMTPA id 850B2211B5; Fri, 1 Dec 2023 15:55:55 +0100 (CET) From: Francesco Dolcini To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Joao Paulo Goncalves , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Francesco Dolcini Subject: [PATCH v2 1/3] arm64: dts: ti: verdin-am62: improve spi1 chip-select pinctrl Date: Fri, 1 Dec 2023 15:55:49 +0100 Message-Id: <20231201145551.23337-2-francesco@dolcini.it> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231201145551.23337-1-francesco@dolcini.it> References: <20231201145551.23337-1-francesco@dolcini.it> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Fri, 01 Dec 2023 06:56:09 -0800 (PST) From: Joao Paulo Goncalves Verdin SPI_1 interface has a dedicated hardware controlled chip select that is currently configured in the same pinctrl group as MISO/MOSI/CLK, however it is possible that it can be used only as a standard GPIO be it a chip select or not. To maximize flexibility and avoid duplication in the carrier board dts files move the SPI_1 CS in a dedicated pinctrl and also adds an additional pinctrl to simplify using SPI_1 CS as a GPIO. Signed-off-by: Joao Paulo Goncalves Signed-off-by: Francesco Dolcini --- arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi index 5db52f237253..6a06724b6d16 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -233,6 +233,13 @@ AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ >; }; + /* Verdin SPI_1 CS as GPIO */ + pinctrl_qspi1_io4_gpio: main-gpio0-7-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x001c, PIN_INPUT, 7) /* (J23) OSPI0_D4.GPIO0_7 */ /* SODIMM 202 */ + >; + }; + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { pinctrl-single,pins = < @@ -599,12 +606,18 @@ AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ /* SODIMM 211 */ pinctrl_spi1: main-spi1-default-pins { pinctrl-single,pins = < AM62X_IOPAD(0x0020, PIN_INPUT, 1) /* (J25) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ - AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ AM62X_IOPAD(0x0024, PIN_INPUT, 1) /* (H25) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ AM62X_IOPAD(0x0028, PIN_INPUT, 1) /* (J22) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ >; }; + /* Verdin SPI_1 CS */ + pinctrl_spi1_cs0: main-spi1-cs0-default-pins { + pinctrl-single,pins = < + AM62X_IOPAD(0x001c, PIN_INPUT, 1) /* (J23) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ + >; + }; + /* ETH_25MHz_CLK */ pinctrl_eth_clock: main-system-clkout0-default-pins { pinctrl-single,pins = < @@ -1278,7 +1291,7 @@ &main_mcan0 { /* Verdin SPI_1 */ &main_spi1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi1>; + pinctrl-0 = <&pinctrl_spi1>, <&pinctrl_spi1_cs0>; ti,pindir-d0-out-d1-in; status = "disabled"; }; -- 2.25.1