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Date:   Sat, 2 Dec 2023 19:28:10 +0800
From:   Jisheng Zhang <jszhang@kernel.org>
To:     Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>
Cc:     linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 0/2] riscv: enable EFFICIENT_UNALIGNED_ACCESS and
 DCACHE_WORD_ACCESS
Message-ID: <ZWsUyjEx1fmXQEfW@xhacker>
References: <20231202111822.3569-1-jszhang@kernel.org>
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On Sat, Dec 02, 2023 at 07:18:20PM +0800, Jisheng Zhang wrote:
> Some riscv implementations such as T-HEAD's C906, C908, C910 and C920
> supports efficient unaligned access, for performance reason we want
> to enable HAVE_EFFICIENT_UNALIGNED_ACCESS on these platforms. To
> avoid performance regressions on other non efficient unaligned access
> platforms, HAVE_EFFICIENT_UNALIGNED_ACCESS can't be globaly selected.
> 
> To solve this problem, runtime code patching based on the detected
> speed is a good solution. But that's not easy, it involves lots of
> work to modify vairous subsystems such as net, mm, lib and so on.
> This can be done step by step.

Adding something as below here can make the series more clear:
So let's take an easier solution: add support to efficient unaligned
access and hide the support under NONPORTABLE.

> 
> patch1 introduces RISCV_EFFICIENT_UNALIGNED_ACCESS which depends on
> NONPORTABLE, if users know during config time that the kernel will be
> only run on those efficient unaligned access hw platforms, they can
> enable it. Obviously, generic unified kernel Image should enable it.

typo: s/should/shouldn't

> 
> patch2 adds support DCACHE_WORD_ACCESS when MMU and
> RISCV_EFFICIENT_UNALIGNED_ACCESS.
> 
> Below test program and step shows how much performance can be improved:
> 
>  $ cat tt.c
>  #include <sys/types.h>
>  #include <sys/stat.h>
>  #include <unistd.h>
> 
>  #define ITERATIONS 1000000
> 
>  #define PATH "123456781234567812345678123456781"
> 
>  int main(void)
>  {
>          unsigned long i;
>          struct stat buf;
> 
>          for (i = 0; i < ITERATIONS; i++)
>                  stat(PATH, &buf);
> 
>          return 0;
>  }
> 
>  $ gcc -O2 tt.c
>  $ touch 123456781234567812345678123456781
>  $ time ./a.out
> 
> Per my test on T-HEAD C910 platforms, the above test performance is
> improved by about 7.5%.
> 
> 
> Jisheng Zhang (2):
>   riscv: introduce RISCV_EFFICIENT_UNALIGNED_ACCESS
>   riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW
> 
>  arch/riscv/Kconfig                      | 13 +++++++++++
>  arch/riscv/include/asm/asm-extable.h    | 15 ++++++++++++
>  arch/riscv/include/asm/word-at-a-time.h | 23 ++++++++++++++++++
>  arch/riscv/mm/extable.c                 | 31 +++++++++++++++++++++++++
>  4 files changed, 82 insertions(+)
> 
> -- 
> 2.42.0
> 
> 
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