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Date:   Mon, 4 Dec 2023 16:50:35 +0800
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Subject: Re: [PATCH v7 26/26] KVM: nVMX: Enable CET support for nested guest
Content-Language: en-US
To:     Maxim Levitsky <mlevitsk@redhat.com>
CC:     <seanjc@google.com>, <pbonzini@redhat.com>,
        <dave.hansen@intel.com>, <kvm@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <peterz@infradead.org>,
        <chao.gao@intel.com>, <rick.p.edgecombe@intel.com>,
        <john.allen@amd.com>
References: <20231124055330.138870-1-weijiang.yang@intel.com>
 <20231124055330.138870-27-weijiang.yang@intel.com>
 <2e280f545e8b15500fc4a2a77f6000a51f6f8bbd.camel@redhat.com>
From:   "Yang, Weijiang" <weijiang.yang@intel.com>
In-Reply-To: <2e280f545e8b15500fc4a2a77f6000a51f6f8bbd.camel@redhat.com>
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 =?utf-8?B?S2Q0b1EwQUl3RGJLNzdLUWdnb0Q3ZnB3WFVVL2VkUHh1ZTljK2pUMHlWV3dn?=
 =?utf-8?B?RzEzTC95cDJ2aFY4dkdqeXN1YmhSeWJ6STY5OHEvRm4rSnR3aXBsczdWVk9v?=
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 =?utf-8?B?NEhQRlRrRDU4M2xaRGcybndpcGpEM0NjUGsyWlVpcldjTXgzWWp1c0Y1Sk5r?=
 =?utf-8?B?c3FuUmg2bmZ2bDQxK2tNQmZoc29UMkhacUorVTdWRmNMT2RobnUxRmJqT2dh?=
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 =?utf-8?B?YmwvU0JGaFV3N3BVcVg5Wi9jNXMyTUpSanlsT3VEN21IM3FzTnBKZTZZQTRh?=
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 =?utf-8?B?dHBvN1F3bVRZdUZFVWZaejlDY1g2elF6akxuZldLWkg3a2VTWTVWM0xNUm1n?=
 =?utf-8?B?SzVLd3pmUHMzT1NJa0xObkl0UGFlQm1SVEFtcCs3TWgrZFlaZlZESlBxSHBr?=
 =?utf-8?B?K1ArQ05YTUM3SzZGcmtUZU9TUUR0N1l4WHJPbGdaRmpEK1lEZXdDeHV3S2Q1?=
 =?utf-8?B?ejJ6MndoVTRGb3RXZTlOTVlJMU5TdkJiM0locndXanVMdldKN2g2VzM5Z09M?=
 =?utf-8?B?SGxzQVFoSTRSK2NQeVRkUWx3MFpFZ1o3Z2pCM2ZHYVdONUl2VWxpa082OHMz?=
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 =?utf-8?B?MFFBSE5jaCtGRHVWemhrVjM4Y0VHZU9xa2VHS2tBZ0tjM2FCVUU5WXR0Umo2?=
 =?utf-8?B?K2ZXYlZxdDFOT2c3NjRzbFNrY3ZwcFN0UkZPYjNCdDBuOWx5dmZoV095aGFI?=
 =?utf-8?B?UUFsU3I5MnpkdWhxRVVPajNVS2ROaE5VRnVZNEF4UW51OU1XNUQ4aFF2ZG5G?=
 =?utf-8?B?RXhlVHd1Q3JZdGxnTzE2SXhwV1NtMHZnUklrTXJhbkdtTlFWMFoxUm01RGVX?=
 =?utf-8?B?S29vQ2o4eWNBZTF4OHpWeW54ZmI0MWpSbDNFUlVZbjlmNlZHYTU1ejhZcnRr?=
 =?utf-8?B?YyswTXpqMTJmOFdiaXhoMTY0TlBTUURNL09jczF6N3k2d3djaExrYWhVbk5E?=
 =?utf-8?B?V2lncXN5RkROc0tlSlFQN1NGNUxmMEdsU3V1MXVXT3VYQXprTFIvdnEwUGdZ?=
 =?utf-8?B?YkZ5SUIzdHFHYy9SOGN0cjFmcGJyL2xOUjB0R2xQN3dOQkYyVHJPUDd1TFlX?=
 =?utf-8?B?bHIvNFU4aHM4UmtOdldOejNSaUVXcjM0YzlaVmF3TWgvRTVkYkdvRlhlWWJt?=
 =?utf-8?B?RDZmTS9kM1lwN0VXWnZDbll3KzY3OTc3MGVNbUc4aW0zanMxdHpNMjMzVzRG?=
 =?utf-8?B?REdSY2NwNkM1RTlhdVloNjlnRjdUWXlYQVlMWm5DdUVkWnA1K1laYVp0UTNG?=
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On 12/1/2023 1:53 AM, Maxim Levitsky wrote:
> On Fri, 2023-11-24 at 00:53 -0500, Yang Weijiang wrote:
>> Set up CET MSRs, related VM_ENTRY/EXIT control bits and fixed CR4 setting
>> to enable CET for nested VM.
>>
>> Note, generally L1 VMM only touches CET VMCS fields when live migration or
>> vmcs_{read,write}() to the fields happens, so the fields only need to be
>> synced in these "rare" cases.
> To be honest we can't assume anything about L1, but what we can assume
>
> is that if vmcs12 field is not shadowed, then L1 vmwrite/vmread will
> be always intercepted and during the interception the fields can be synced,
> however I studied this area long ago and I might be mistaken.

The changelog wording failed to express what I meant to say:
vmcs12 and vmcs02 should be synced to reflect the correct CET states L1 or L2 are expected
to see. In LM case, the nested CET states should also be synced between L1 or L2 via the
control structures.

Will reword them, thanks for pointing it out!
>>   And here only considers the case that L1 VMM
>> has set VM_ENTRY_LOAD_CET_STATE in its VMCS vm_entry_controls as it's the
>> common usage.
>>
>> Suggested-by: Chao Gao <chao.gao@intel.com>
>> Signed-off-by: Yang Weijiang <weijiang.yang@intel.com>
>> ---
>>   arch/x86/kvm/vmx/nested.c | 48 +++++++++++++++++++++++++++++++++++++--
>>   arch/x86/kvm/vmx/vmcs12.c |  6 +++++
>>   arch/x86/kvm/vmx/vmcs12.h | 14 +++++++++++-
>>   arch/x86/kvm/vmx/vmx.c    |  2 ++
>>   4 files changed, 67 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c
>> index d8c32682ca76..965173650542 100644
>> --- a/arch/x86/kvm/vmx/nested.c
>> +++ b/arch/x86/kvm/vmx/nested.c
>> @@ -660,6 +660,28 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu,
>>   	nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
>>   					 MSR_IA32_FLUSH_CMD, MSR_TYPE_W);
>>   
>> +	/* Pass CET MSRs to nested VM if L0 and L1 are set to pass-through. */
>> +	nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
>> +					 MSR_IA32_U_CET, MSR_TYPE_RW);
>> +
>> +	nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
>> +					 MSR_IA32_S_CET, MSR_TYPE_RW);
>> +
>> +	nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
>> +					 MSR_IA32_PL0_SSP, MSR_TYPE_RW);
>> +
>> +	nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
>> +					 MSR_IA32_PL1_SSP, MSR_TYPE_RW);
>> +
>> +	nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
>> +					 MSR_IA32_PL2_SSP, MSR_TYPE_RW);
>> +
>> +	nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
>> +					 MSR_IA32_PL3_SSP, MSR_TYPE_RW);
>> +
>> +	nested_vmx_set_intercept_for_msr(vmx, msr_bitmap_l1, msr_bitmap_l0,
>> +					 MSR_IA32_INT_SSP_TAB, MSR_TYPE_RW);
>> +
>>   	kvm_vcpu_unmap(vcpu, &vmx->nested.msr_bitmap_map, false);
>>   
>>   	vmx->nested.force_msr_bitmap_recalc = false;
>> @@ -2469,6 +2491,18 @@ static void prepare_vmcs02_rare(struct vcpu_vmx *vmx, struct vmcs12 *vmcs12)
>>   		if (kvm_mpx_supported() && vmx->nested.nested_run_pending &&
>>   		    (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS))
>>   			vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
>> +
>> +		if (vmx->nested.nested_run_pending &&
> I don't think that nested.nested_run_pending check is needed.
> prepare_vmcs02_rare is not going to be called unless the nested run is pending.

But there're other paths along to call prepare_vmcs02_rare(), e.g., vmx_set_nested_state()-> nested_vmx_enter_non_root_mode()-> prepare_vmcs02_rare(), especially when L1 instead of L2 was running. In this case, nested.nested_run_pending == false,
we don't need to update vmcs02's fields at the point until L2 is being resumed.

>> +		    (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_CET_STATE)) {
>> +			if (guest_can_use(&vmx->vcpu, X86_FEATURE_SHSTK)) {
>> +				vmcs_writel(GUEST_SSP, vmcs12->guest_ssp);
>> +				vmcs_writel(GUEST_INTR_SSP_TABLE,
>> +					    vmcs12->guest_ssp_tbl);
>> +			}
>> +			if (guest_can_use(&vmx->vcpu, X86_FEATURE_SHSTK) ||
>> +			    guest_can_use(&vmx->vcpu, X86_FEATURE_IBT))
>> +				vmcs_writel(GUEST_S_CET, vmcs12->guest_s_cet);
>> +		}
>>   	}
>>   
>>   	if (nested_cpu_has_xsaves(vmcs12))
>> @@ -4300,6 +4334,15 @@ static void sync_vmcs02_to_vmcs12_rare(struct kvm_vcpu *vcpu,
>>   	vmcs12->guest_pending_dbg_exceptions =
>>   		vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
>>   
>> +	if (guest_can_use(&vmx->vcpu, X86_FEATURE_SHSTK)) {
>> +		vmcs12->guest_ssp = vmcs_readl(GUEST_SSP);
>> +		vmcs12->guest_ssp_tbl = vmcs_readl(GUEST_INTR_SSP_TABLE);
>> +	}
>> +	if (guest_can_use(&vmx->vcpu, X86_FEATURE_SHSTK) ||
>> +	    guest_can_use(&vmx->vcpu, X86_FEATURE_IBT)) {
>> +		vmcs12->guest_s_cet = vmcs_readl(GUEST_S_CET);
>> +	}
> The above code should be conditional on VM_ENTRY_LOAD_CET_STATE - if the guest (L2) state
> was loaded, then it must be updated on exit - this is usually how VMX works.

I think this is not for L2 VM_ENTRY_LOAD_CET_STATE, it happens in prepare_vmcs02_rare(). IIUC, the guest registers will be saved into VMCS fields unconditionally when vm-exit happens,
so these fields for L2 guest should be synced to L1 unconditionally.

> Also I don't see any mention of usage of VM_EXIT_LOAD_CET_STATE, which if set,
> should reset the L1 CET state to values in 'host_s_cet/host_ssp/host_ssp_tbl'
> (This is also a common theme in VMX - host state is reset to values that the hypervisor
> sets in VMCS, and the hypervisor must care to update these fields itself).

Yes, the host CET states for L1 also should be synced, I'll add the missing part, thanks!

> As a rule of thumb, if you add a field to vmcs12, you should use it somewhere,
> and you should never use it unconditionally, as almost always its use
> depends on entry or exit controls.
>
> Same is true for entry/exit/execution controls - if you add one, you almost
> always have to use it somewhere.

I'll double check if anything is lost in various cases, thanks!

> Best regards,
> 	Maxim Levitsky
>
>> +
>>   	vmx->nested.need_sync_vmcs02_to_vmcs12_rare = false;
>>   }
>>   
>> @@ -6798,7 +6841,7 @@ static void nested_vmx_setup_exit_ctls(struct vmcs_config *vmcs_conf,
>>   		VM_EXIT_HOST_ADDR_SPACE_SIZE |
>>   #endif
>>   		VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
>> -		VM_EXIT_CLEAR_BNDCFGS;
>> +		VM_EXIT_CLEAR_BNDCFGS | VM_EXIT_LOAD_CET_STATE;
>>   	msrs->exit_ctls_high |=
>>   		VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
>>   		VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
>> @@ -6820,7 +6863,8 @@ static void nested_vmx_setup_entry_ctls(struct vmcs_config *vmcs_conf,
>>   #ifdef CONFIG_X86_64
>>   		VM_ENTRY_IA32E_MODE |
>>   #endif
>> -		VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
>> +		VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS |
>> +		VM_ENTRY_LOAD_CET_STATE;
>>   	msrs->entry_ctls_high |=
>>   		(VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER |
>>   		 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL);
>> diff --git a/arch/x86/kvm/vmx/vmcs12.c b/arch/x86/kvm/vmx/vmcs12.c
>> index 106a72c923ca..4233b5ca9461 100644
>> --- a/arch/x86/kvm/vmx/vmcs12.c
>> +++ b/arch/x86/kvm/vmx/vmcs12.c
>> @@ -139,6 +139,9 @@ const unsigned short vmcs12_field_offsets[] = {
>>   	FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
>>   	FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
>>   	FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
>> +	FIELD(GUEST_S_CET, guest_s_cet),
>> +	FIELD(GUEST_SSP, guest_ssp),
>> +	FIELD(GUEST_INTR_SSP_TABLE, guest_ssp_tbl),
>>   	FIELD(HOST_CR0, host_cr0),
>>   	FIELD(HOST_CR3, host_cr3),
>>   	FIELD(HOST_CR4, host_cr4),
>> @@ -151,5 +154,8 @@ const unsigned short vmcs12_field_offsets[] = {
>>   	FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
>>   	FIELD(HOST_RSP, host_rsp),
>>   	FIELD(HOST_RIP, host_rip),
>> +	FIELD(HOST_S_CET, host_s_cet),
>> +	FIELD(HOST_SSP, host_ssp),
>> +	FIELD(HOST_INTR_SSP_TABLE, host_ssp_tbl),
>>   };
>>   const unsigned int nr_vmcs12_fields = ARRAY_SIZE(vmcs12_field_offsets);
>> diff --git a/arch/x86/kvm/vmx/vmcs12.h b/arch/x86/kvm/vmx/vmcs12.h
>> index 01936013428b..3884489e7f7e 100644
>> --- a/arch/x86/kvm/vmx/vmcs12.h
>> +++ b/arch/x86/kvm/vmx/vmcs12.h
>> @@ -117,7 +117,13 @@ struct __packed vmcs12 {
>>   	natural_width host_ia32_sysenter_eip;
>>   	natural_width host_rsp;
>>   	natural_width host_rip;
>> -	natural_width paddingl[8]; /* room for future expansion */
>> +	natural_width host_s_cet;
>> +	natural_width host_ssp;
>> +	natural_width host_ssp_tbl;
>> +	natural_width guest_s_cet;
>> +	natural_width guest_ssp;
>> +	natural_width guest_ssp_tbl;
>> +	natural_width paddingl[2]; /* room for future expansion */
>>   	u32 pin_based_vm_exec_control;
>>   	u32 cpu_based_vm_exec_control;
>>   	u32 exception_bitmap;
>> @@ -292,6 +298,12 @@ static inline void vmx_check_vmcs12_offsets(void)
>>   	CHECK_OFFSET(host_ia32_sysenter_eip, 656);
>>   	CHECK_OFFSET(host_rsp, 664);
>>   	CHECK_OFFSET(host_rip, 672);
>> +	CHECK_OFFSET(host_s_cet, 680);
>> +	CHECK_OFFSET(host_ssp, 688);
>> +	CHECK_OFFSET(host_ssp_tbl, 696);
>> +	CHECK_OFFSET(guest_s_cet, 704);
>> +	CHECK_OFFSET(guest_ssp, 712);
>> +	CHECK_OFFSET(guest_ssp_tbl, 720);
>>   	CHECK_OFFSET(pin_based_vm_exec_control, 744);
>>   	CHECK_OFFSET(cpu_based_vm_exec_control, 748);
>>   	CHECK_OFFSET(exception_bitmap, 752);
>> diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
>> index a1aae8709939..947028ff2e25 100644
>> --- a/arch/x86/kvm/vmx/vmx.c
>> +++ b/arch/x86/kvm/vmx/vmx.c
>> @@ -7734,6 +7734,8 @@ static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
>>   	cr4_fixed1_update(X86_CR4_PKE,        ecx, feature_bit(PKU));
>>   	cr4_fixed1_update(X86_CR4_UMIP,       ecx, feature_bit(UMIP));
>>   	cr4_fixed1_update(X86_CR4_LA57,       ecx, feature_bit(LA57));
>> +	cr4_fixed1_update(X86_CR4_CET,	      ecx, feature_bit(SHSTK));
>> +	cr4_fixed1_update(X86_CR4_CET,	      edx, feature_bit(IBT));
>>   
>>   #undef cr4_fixed1_update
>>   }
>
>