Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35;
From:   Frank Li <Frank.Li@nxp.com>
To:     manivannan.sadhasivam@linaro.org
Cc:     Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev,
        kw@linux.com, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
        linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org,
        minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org,
        roy.zang@nxp.com
Subject: [PATCH v6 2/4] PCI: layerscape: Add suspend/resume for ls1021a
Date:   Mon,  4 Dec 2023 11:08:27 -0500
Message-Id: <20231204160829.2498703-3-Frank.Li@nxp.com>
In-Reply-To: <20231204160829.2498703-1-Frank.Li@nxp.com>
References: <20231204160829.2498703-1-Frank.Li@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?mDdPMbmMSOcHYKEo7vGOnWxzTS++2BbXjrvRfBsk0qt5idOag21jauwdplWo?=
 =?us-ascii?Q?wwbKpxXqK/XliiEj+TG5jLpDvi7R/Y39wTbs+Om0SzuzunKHJwndo0aDKcAi?=
 =?us-ascii?Q?8GtknFNi/a9xkA8yUR4kzmSYk1c7phyYU/OV0HGWUpGklwh6NzQQNnXQAvi9?=
 =?us-ascii?Q?JvZAavM3tm1o5ZjLI5K7783a0hlo/UbCtBKyjy44zKrKdtUUvUF2nfjd+VvM?=
 =?us-ascii?Q?gSWmzBwOj/cnOfZmAbT/mbgvrPptIRbYoqMB+CKh3L3JU3Mv2Ix+Dt/N7jer?=
 =?us-ascii?Q?boZCt6g3F2f8zOiG7AF+nfWjb0Q/Lg2Y7Kwmlk+4fG2mEl8mZT9KzAG+AYlN?=
 =?us-ascii?Q?8V4uh1PiF38YGlDz25s1fKwXr8Af+2tPgRI+f6Uj6EWSoeP+wfPJxxc7z7zY?=
 =?us-ascii?Q?htc/UWWW4HioLP2yjOBxnkNXk2hR8RcoVB44ukOoZX7lNuAqztwJBZ9wU87f?=
 =?us-ascii?Q?8i8pNjWMZ31G3LFABwHXTSFBCcXRD2iHf/gTVAJk6lk7cnyps8Gg/D4y9044?=
 =?us-ascii?Q?97vuqvk8KBix1P7hJwEljeo9KFsqsBjPtaiTxqxvlAhZfFzCuvwbbxVO2vrT?=
 =?us-ascii?Q?1TIIfKlGitSNh258TLBFfuRQmT5WJ7bqaNquYcJDGBT0srXA4c8+95gVQTj8?=
 =?us-ascii?Q?Djo8VtWeJRXG1mK1XdyXYNqsJkv58pX3JMmBsVugp4lIBmBbXkB0FlC6U71w?=
 =?us-ascii?Q?+adN90t9ie32BpXixUFWJ3nBdasHxw4ZDGsRxX0eJjy7EZy2nP0rGGsFu/Hq?=
 =?us-ascii?Q?HIpgAF61kI+RglKeggm3CgL0xxuJ+ffEbhV7oCYHKTqTpLgtlSsMJfpQG3ve?=
 =?us-ascii?Q?Trk+9DoAldClDT1K9ux3ecK7RCt/k710UbKZaxDrLNevXFMTnyDOPDD3+l/G?=
 =?us-ascii?Q?9fMKy6HrAqM4FtclF93b1Jb1eTK+MFD1ShTpurHMQwuHcfrfQ9H2J0CpgTVp?=
 =?us-ascii?Q?cZ2MTTskP/Rg5uN0xVI7Q4P4PfsrC9029pWNc8WPR0dDkfg+vyhHsHZ4ZS+s?=
 =?us-ascii?Q?cmvj7Vhw3N19/b6bIEKMJOHZfBrMf9/n0Vmvan7A2aPYPDM7rdap3BzhdN7o?=
 =?us-ascii?Q?um6KElqHeQA+4i4KeXoVKLkoJms4EMfYpjYutbRPoMc1cuxEAM2ZnjpJiSvz?=
 =?us-ascii?Q?buvwxbydVTHfxd2k/YudDUBaG1XgIEE7qYzKAudvIc/nIKmqNhoW5TLaj0z/?=
 =?us-ascii?Q?tE/LdG6439W4r4EQNqsrnzi8F+SRxwbUad3zw5UwBsBpq170yS8x42nmSDu9?=
 =?us-ascii?Q?9sR9UV9DCbbn1P/B4tvxViIfwtNGFgwMDgl8flF360sPtNyB9GGuKu8I460t?=
 =?us-ascii?Q?uyRuWXSt6+ELP/g66MpEUbNE3LOLdOCuOWdlEjNsJi+TyPyGxpPSyIQEqiLU?=
 =?us-ascii?Q?X4GfhtcJfT9LUJltxKkxmK6m6p1MQE53/EBHJicqAKVLZawtNZIIQtWiV2SJ?=
 =?us-ascii?Q?PmSd4O2YOkiv7r0jAEzPuuNqL8Dl9WTdEgr6ckF41R5KMZMlJvDBXWxVVj4m?=
 =?us-ascii?Q?njkBDyOHdmp6x9X5GRGeXG9NztHe1/haxJir4OMAo3zWE2BWvZTwtgOWeCpS?=
 =?us-ascii?Q?n515uDveIxsfjxmpGk4RHuGWkwQBl9oX2Vj0jPQE?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: c32978ae-40cb-4e11-9511-08dbf4e35135
X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2023 16:08:56.2185
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 8t3aJfPrbmn8FfH2xo75WxxLD+Lo+LVezPPFLy1vSyc30UmkxqZu/8Mcjp84cL76cntvldwz5zIenhRl37f0Bw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB8057
X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID,
	DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,
	SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable
	autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 04 Dec 2023 08:09:33 -0800 (PST)

Add suspend/resume support for Layerscape LS1021a.

In the suspend path, PME_Turn_Off message is sent to the endpoint to
transition the link to L2/L3_Ready state. In this SoC, there is no way to
check if the controller has received the PME_To_Ack from the endpoint or
not. So to be on the safer side, the driver just waits for
PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF
bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3
state depending on the VAUX supply.

In the resume path, the link is brought back from L2 to L0 by doing a
software reset.

Acked-by: Roy Zang <Roy.Zang@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---

Notes:
    Change from v5 to v6
    - remove reduntant pci->pp.ops = &ls_pcie_host_ops;
    Change from v4 to v5
    - update comit message
    - remove a empty line
    - use comments
    /* Reset the PEX wrapper to bring the link out of L2 */
    - pci->pp.ops = pcie->drvdata->ops,
    ls_pcie_host_ops to the "ops" member of layerscape_drvdata.
    - don't set pcie->scfg = NULL at error path
    
    Change from v3 to v4
    - update commit message.
    - it is reset a glue logic part for PCI controller.
    - use regmap_write_bits() to reduce code change.
    
    Change from v2 to v3
    - update according to mani's feedback
    change from v1 to v2
    - change subject 'a' to 'A'

 drivers/pci/controller/dwc/pci-layerscape.c | 83 ++++++++++++++++++++-
 1 file changed, 80 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
index aea89926bcc4f..711563777aeba 100644
--- a/drivers/pci/controller/dwc/pci-layerscape.c
+++ b/drivers/pci/controller/dwc/pci-layerscape.c
@@ -35,11 +35,19 @@
 #define PF_MCR_PTOMR		BIT(0)
 #define PF_MCR_EXL2S		BIT(1)
 
+/* LS1021A PEXn PM Write Control Register */
+#define SCFG_PEXPMWRCR(idx)	(0x5c + (idx) * 0x64)
+#define PMXMTTURNOFF		BIT(31)
+#define SCFG_PEXSFTRSTCR	0x190
+#define PEXSR(idx)		BIT(idx)
+
 #define PCIE_IATU_NUM		6
 
 struct ls_pcie_drvdata {
 	const u32 pf_off;
+	const struct dw_pcie_host_ops *ops;
 	int (*exit_from_l2)(struct dw_pcie_rp *pp);
+	bool scfg_support;
 	bool pm_support;
 };
 
@@ -47,6 +55,8 @@ struct ls_pcie {
 	struct dw_pcie *pci;
 	const struct ls_pcie_drvdata *drvdata;
 	void __iomem *pf_base;
+	struct regmap *scfg;
+	int index;
 	bool big_endian;
 };
 
@@ -171,18 +181,70 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp)
 	return 0;
 }
 
+static void scfg_pcie_send_turnoff_msg(struct regmap *scfg, u32 reg, u32 mask)
+{
+	/* Send PME_Turn_Off message */
+	regmap_write_bits(scfg, reg, mask, mask);
+
+	/*
+	 * There is no specific register to check for PME_To_Ack from endpoint.
+	 * So on the safe side, wait for PCIE_PME_TO_L2_TIMEOUT_US.
+	 */
+	mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000);
+
+	/*
+	 * Layerscape hardware reference manual recommends clearing the PMXMTTURNOFF bit
+	 * to complete the PME_Turn_Off handshake.
+	 */
+	regmap_write_bits(scfg, reg, mask, 0);
+}
+
+static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+
+	scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), PMXMTTURNOFF);
+}
+
+static int scfg_pcie_exit_from_l2(struct regmap *scfg, u32 reg, u32 mask)
+{
+	/* Reset the PEX wrapper to bring the link out of L2 */
+	regmap_write_bits(scfg, reg, mask, mask);
+	regmap_write_bits(scfg, reg, mask, 0);
+
+	return 0;
+}
+
+static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+
+	return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index));
+}
+
 static const struct dw_pcie_host_ops ls_pcie_host_ops = {
 	.host_init = ls_pcie_host_init,
 	.pme_turn_off = ls_pcie_send_turnoff_msg,
 };
 
+static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = {
+	.host_init = ls_pcie_host_init,
+	.pme_turn_off = ls1021a_pcie_send_turnoff_msg,
+};
+
 static const struct ls_pcie_drvdata ls1021a_drvdata = {
-	.pm_support = false,
+	.pm_support = true,
+	.scfg_support = true,
+	.ops = &ls1021a_pcie_host_ops,
+	.exit_from_l2 = ls1021a_pcie_exit_from_l2,
 };
 
 static const struct ls_pcie_drvdata layerscape_drvdata = {
 	.pf_off = 0xc0000,
 	.pm_support = true,
+	.ops = &ls_pcie_host_ops,
 	.exit_from_l2 = ls_pcie_exit_from_l2,
 };
 
@@ -205,6 +267,8 @@ static int ls_pcie_probe(struct platform_device *pdev)
 	struct dw_pcie *pci;
 	struct ls_pcie *pcie;
 	struct resource *dbi_base;
+	u32 index[2];
+	int ret;
 
 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
 	if (!pcie)
@@ -217,9 +281,8 @@ static int ls_pcie_probe(struct platform_device *pdev)
 	pcie->drvdata = of_device_get_match_data(dev);
 
 	pci->dev = dev;
-	pci->pp.ops = &ls_pcie_host_ops;
-
 	pcie->pci = pci;
+	pci->pp.ops = pcie->drvdata->ops;
 
 	dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 	pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
@@ -230,6 +293,20 @@ static int ls_pcie_probe(struct platform_device *pdev)
 
 	pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off;
 
+	if (pcie->drvdata->scfg_support) {
+		pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg");
+		if (IS_ERR(pcie->scfg)) {
+			dev_err(dev, "No syscfg phandle specified\n");
+			return PTR_ERR(pcie->scfg);
+		}
+
+		ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2);
+		if (ret)
+			return ret;
+
+		pcie->index = index[1];
+	}
+
 	if (!ls_pcie_is_bridge(pcie))
 		return -ENODEV;
 
-- 
2.34.1