Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38;
From:   Frank Li <Frank.Li@nxp.com>
To:     manivannan.sadhasivam@linaro.org
Cc:     Frank.Li@nxp.com, bhelgaas@google.com, imx@lists.linux.dev,
        kw@linux.com, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
        linuxppc-dev@lists.ozlabs.org, lpieralisi@kernel.org,
        minghuan.Lian@nxp.com, mingkai.hu@nxp.com, robh@kernel.org,
        roy.zang@nxp.com
Subject: [PATCH v6 4/4] PCI: layerscape: Add suspend/resume for ls1043a
Date:   Mon,  4 Dec 2023 11:08:29 -0500
Message-Id: <20231204160829.2498703-5-Frank.Li@nxp.com>
In-Reply-To: <20231204160829.2498703-1-Frank.Li@nxp.com>
References: <20231204160829.2498703-1-Frank.Li@nxp.com>
Content-Transfer-Encoding: 8bit
Content-Type: text/plain
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?wazukdBV3FKFMAbcBiDbf33+ZJ/ToHfcd5dBck4iULRsBYSFUVAaWo5ehD0+?=
 =?us-ascii?Q?lhwLD09mZSLQwIQUL8kpPxG9yfs1wy+6Q3izdI+M7Ed681uWMYX3Csso9+zP?=
 =?us-ascii?Q?o056DY/sxkz68bH5t7W07XVwzAPJWZHtjQ1Ivw6e9oLZOlCiSVZZtpUPGFVJ?=
 =?us-ascii?Q?JcrkzwhZGwtQiMWVLiZJQji7IaDrNVxvjaRoaY844sm2jHB+22xY4pzBmNDU?=
 =?us-ascii?Q?m69WeUokuSJnxM4d7Ac/11LP/7K8rZqMQwm7+OaOxOHuSEMTAfyY/tvJQNdM?=
 =?us-ascii?Q?YFZHL+g5GIV2UNyo9M+UYpQXfXl9/okLJzY5lF3ImbBThdTX8u9oFWx4A//V?=
 =?us-ascii?Q?GP0xZiBdR+OQfW4lY22QbfYLP8cbh3e8sqmUNouLHPsSMzm+dFwHD1d3CZKr?=
 =?us-ascii?Q?VnoYXyVOnH9UaiPBTeYfyBtQLXD9sMLBA/Uc7wtMA/n8qiZ7pycTM9GuDCn/?=
 =?us-ascii?Q?l6Q2Um1yRu8+gFn+GwBukx54c137fB9TNmt9FJSVieUPPlvg3/8L63OOXNh0?=
 =?us-ascii?Q?TCzuOL10m98MrTp+4iQOQmRy6H3nuWtDkfzx9AzF65YdFCLNhmFrVDyvpxR8?=
 =?us-ascii?Q?n46HNx9w9wIKEeI4aDjjj5JVzbsuun9f76k1EpL1SaxIksRmL/jg9yttWvo9?=
 =?us-ascii?Q?5P2AvXfqbUoQ502bxh5Dh8TQbmKrpXPy+lO5gumhh3cwxyf8OkdpEooikfNc?=
 =?us-ascii?Q?OKTi2vFD57Rfu2LGqPiVi8MDo51nV44/7YMgIB8FvSD/Wk7tSmKATilp+mXa?=
 =?us-ascii?Q?sZOGQJXiu8E4zoVzTOLaVqeWKpgdqDb138jE0EIU9Fj8O6pvpT3+qDLBt2fR?=
 =?us-ascii?Q?G94TA3RVllZHOC9BtWZGDqU/lUOpqpufvVPmBO6cosqZcGYhWrdmAjhpF9o5?=
 =?us-ascii?Q?WkpRtYGjzVRI0p/SfiVeFMh2whpcjec615b7jEce273CMWy3hKlqgWkEIsyd?=
 =?us-ascii?Q?lY2JBtCM0lj0Dg5FYfH5YijZhbkM3VJffl2MQtk3x9JT2OTCEYq0TTd2YX8u?=
 =?us-ascii?Q?rKOnkBG5Yvcl/O2IutzNCtZf3r/K7sNdYAGTmPFNlhIVbNuKxJRAyW/HT9h7?=
 =?us-ascii?Q?JDI/LnAs9/ey9fF/8H2ZqKdEYZOlUEuly3106SgGxfBndEAqvena05H/z3XK?=
 =?us-ascii?Q?EAnmVMMfDmldcjJpsDUY/1UZuL/mnDAdtrlNb8TwdsDccHY2pOrX/B5Ons9o?=
 =?us-ascii?Q?yGkaS952+yfu57uEXz+bchMNE6RhyVkjV0ElVgRtJkd3WinGz5tFvBfDXt7O?=
 =?us-ascii?Q?OZBUXKFqpW2Ve6Vvdh6bUdgELtgZ18/QiZQCIz6tLwKVSGitu9iAP4iABE8R?=
 =?us-ascii?Q?xTHi04G5I+bTaqYQIW2JiLiZHkszc+rpZ7YeJI6AlfChF3fi5D81bXqrDlzJ?=
 =?us-ascii?Q?I6OTJGpaPzfUJ5WE3V1ExBOJ+9SvBRSS0hSjgdWOFQSwuEm2EMaZoyHsfkKF?=
 =?us-ascii?Q?meS+kl/opOq1qBYHSJ/W6hI3yjqtldJbhat8cyy6pBvtMREWnHn3cJYfC1vD?=
 =?us-ascii?Q?ACUoMUdDWvR/EamoefD5/KfkLACdQwkA2yg4ZfhFHqWifs072eXUlI/n5dVV?=
 =?us-ascii?Q?B0Uc14g5H/2F9kuEjDUJ6SSAGNw3/66K7M1xWayb?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: c9d7ed75-10f3-475c-c2a7-08dbf4e35593
X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2023 16:09:03.5363
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: warSZXDLyiFS6+GMyL6cXJVfI9dplmdgqUFKMCbgiXF0kVDPGOJE21Jwusp0hS1UNGWcweShiAl3HuXgciEz9g==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB8057
X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID,
	DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,
	SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable
	autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org
X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Mon, 04 Dec 2023 08:09:38 -0800 (PST)

Add suspend/resume support for Layerscape LS1043a.

In the suspend path, PME_Turn_Off message is sent to the endpoint to
transition the link to L2/L3_Ready state. In this SoC, there is no way to
check if the controller has received the PME_To_Ack from the endpoint or
not. So to be on the safer side, the driver just waits for
PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF
bit to complete the PME_Turn_Off handshake. Then the link would enter L2/L3
state depending on the VAUX supply.

In the resume path, the link is brought back from L2 to L0 by doing a
software reset.

Acked-by: Roy Zang <Roy.Zang@nxp.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---

Notes:
    Chagne from v5 to v6
    - none
    Change from v4 to v5
    - update commit message
    - use comments
    /* Reset the PEX wrapper to bring the link out of L2 */
    
    Change from v3 to v4
    - Call scfg_pcie_send_turnoff_msg() shared with ls1021a
    - update commit message
    
    Change from v2 to v3
    - Remove ls_pcie_lut_readl(writel) function
    
    Change from v1 to v2
    - Update subject 'a' to 'A'

 drivers/pci/controller/dwc/pci-layerscape.c | 63 ++++++++++++++++++++-
 1 file changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
index f3dfb70066fb7..7cdada200de7e 100644
--- a/drivers/pci/controller/dwc/pci-layerscape.c
+++ b/drivers/pci/controller/dwc/pci-layerscape.c
@@ -41,6 +41,15 @@
 #define SCFG_PEXSFTRSTCR	0x190
 #define PEXSR(idx)		BIT(idx)
 
+/* LS1043A PEX PME control register */
+#define SCFG_PEXPMECR		0x144
+#define PEXPME(idx)		BIT(31 - (idx) * 4)
+
+/* LS1043A PEX LUT debug register */
+#define LS_PCIE_LDBG	0x7fc
+#define LDBG_SR		BIT(30)
+#define LDBG_WE		BIT(31)
+
 #define PCIE_IATU_NUM		6
 
 struct ls_pcie_drvdata {
@@ -224,6 +233,45 @@ static int ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp)
 	return scfg_pcie_exit_from_l2(pcie->scfg, SCFG_PEXSFTRSTCR, PEXSR(pcie->index));
 }
 
+static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+
+	scfg_pcie_send_turnoff_msg(pcie->scfg, SCFG_PEXPMECR, PEXPME(pcie->index));
+}
+
+static int ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+	struct ls_pcie *pcie = to_ls_pcie(pci);
+	u32 val;
+
+	/*
+	 * Reset the PEX wrapper to bring the link out of L2.
+	 * LDBG_WE: allows the user to have write access to the PEXDBG[SR] for both setting and
+	 *	    clearing the soft reset on the PEX module.
+	 * LDBG_SR: When SR is set to 1, the PEX module enters soft reset.
+	 */
+	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
+	val |= LDBG_WE;
+	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
+
+	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
+	val |= LDBG_SR;
+	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
+
+	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
+	val &= ~LDBG_SR;
+	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
+
+	val = ls_pcie_pf_lut_readl(pcie, LS_PCIE_LDBG);
+	val &= ~LDBG_WE;
+	ls_pcie_pf_lut_writel(pcie, LS_PCIE_LDBG, val);
+
+	return 0;
+}
+
 static const struct dw_pcie_host_ops ls_pcie_host_ops = {
 	.host_init = ls_pcie_host_init,
 	.pme_turn_off = ls_pcie_send_turnoff_msg,
@@ -241,6 +289,19 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = {
 	.exit_from_l2 = ls1021a_pcie_exit_from_l2,
 };
 
+static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = {
+	.host_init = ls_pcie_host_init,
+	.pme_turn_off = ls1043a_pcie_send_turnoff_msg,
+};
+
+static const struct ls_pcie_drvdata ls1043a_drvdata = {
+	.pf_lut_off = 0x10000,
+	.pm_support = true,
+	.scfg_support = true,
+	.ops = &ls1043a_pcie_host_ops,
+	.exit_from_l2 = ls1043a_pcie_exit_from_l2,
+};
+
 static const struct ls_pcie_drvdata layerscape_drvdata = {
 	.pf_lut_off = 0xc0000,
 	.pm_support = true,
@@ -252,7 +313,7 @@ static const struct of_device_id ls_pcie_of_match[] = {
 	{ .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata },
 	{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata },
 	{ .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata },
-	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata },
+	{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata },
 	{ .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata },
 	{ .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata },
 	{ .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata },
-- 
2.34.1