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Message-ID: <e16ac596-353c-385b-a331-78c9261474a3@quicinc.com>
Date:   Mon, 4 Dec 2023 22:57:38 +0530
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Subject: Re: [PATCH v5 2/3] arm64: dts: qcom: sc7280: Add UFS nodes for sc7280
 soc
Content-Language: en-US
To:     Luca Weiss <luca.weiss@fairphone.com>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Manivannan Sadhasivam <mani@kernel.org>,
        Alim Akhtar <alim.akhtar@samsung.com>,
        Avri Altman <avri.altman@wdc.com>,
        Bart Van Assche <bvanassche@acm.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        <cros-qcom-dts-watchers@chromium.org>
CC:     <~postmarketos/upstreaming@lists.sr.ht>,
        <phone-devel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
        <linux-scsi@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>
References: <20231204-sc7280-ufs-v5-0-926ceed550da@fairphone.com>
 <20231204-sc7280-ufs-v5-2-926ceed550da@fairphone.com>
 <621388b9-dcee-4af2-9763-e5d623d722b7@quicinc.com>
 <CXFJNBNKTRHH.2CS6TO2MEGJWL@fairphone.com>
From:   Nitin Rawat <quic_nitirawa@quicinc.com>
In-Reply-To: <CXFJNBNKTRHH.2CS6TO2MEGJWL@fairphone.com>
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On 12/4/2023 5:51 PM, Luca Weiss wrote:
> On Mon Dec 4, 2023 at 1:15 PM CET, Nitin Rawat wrote:
>>
>>
>> On 12/4/2023 3:54 PM, Luca Weiss wrote:
>>> From: Nitin Rawat <quic_nitirawa@quicinc.com>
>>>
>>> Add UFS host controller and PHY nodes for sc7280 soc.
>>>
>>> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>>> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # QCM6490 FP5
>>> [luca: various cleanups and additions as written in the cover letter]
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>>    arch/arm64/boot/dts/qcom/sc7280.dtsi | 74 +++++++++++++++++++++++++++++++++++-
>>>    1 file changed, 73 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> index 04bf85b0399a..8b08569f2191 100644
>>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>>> @@ -15,6 +15,7 @@
>>>    #include <dt-bindings/dma/qcom-gpi.h>
>>>    #include <dt-bindings/firmware/qcom,scm.h>
>>>    #include <dt-bindings/gpio/gpio.h>
>>> +#include <dt-bindings/interconnect/qcom,icc.h>
>>>    #include <dt-bindings/interconnect/qcom,osm-l3.h>
>>>    #include <dt-bindings/interconnect/qcom,sc7280.h>
>>>    #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> @@ -906,7 +907,7 @@ gcc: clock-controller@100000 {
>>>    			clocks = <&rpmhcc RPMH_CXO_CLK>,
>>>    				 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
>>>    				 <0>, <&pcie1_phy>,
>>> -				 <0>, <0>, <0>,
>>> +				 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>,
>>>    				 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>>>    			clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
>>>    				      "pcie_0_pipe_clk", "pcie_1_pipe_clk",
>>> @@ -2238,6 +2239,77 @@ pcie1_phy: phy@1c0e000 {
>>>    			status = "disabled";
>>>    		};
>>>    
>>> +		ufs_mem_hc: ufs@1d84000 {
>>> +			compatible = "qcom,sc7280-ufshc", "qcom,ufshc",
>>> +				     "jedec,ufs-2.0";
>>> +			reg = <0x0 0x01d84000 0x0 0x3000>;
>>> +			interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
>>> +			phys = <&ufs_mem_phy>;
>>> +			phy-names = "ufsphy";
>>> +			lanes-per-direction = <2>;
>>> +			#reset-cells = <1>;
>>> +			resets = <&gcc GCC_UFS_PHY_BCR>;
>>> +			reset-names = "rst";
>>> +
>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
>>> +			required-opps = <&rpmhpd_opp_nom>;
>>> +
>>> +			iommus = <&apps_smmu 0x80 0x0>;
>>> +			dma-coherent;
>>> +
>>> +			interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS
>>> +					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>>> +					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
>>> +					 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>;
>>> +			interconnect-names = "ufs-ddr", "cpu-ufs";
>>> +
>>> +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
>>> +				 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
>>> +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
>>> +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
>>> +				 <&rpmhcc RPMH_CXO_CLK>,
>>> +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
>>> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
>>> +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
>>> +			clock-names = "core_clk",
>>> +				      "bus_aggr_clk",
>>> +				      "iface_clk",
>>> +				      "core_clk_unipro",
>>> +				      "ref_clk",
>>> +				      "tx_lane0_sync_clk",
>>> +				      "rx_lane0_sync_clk",
>>> +				      "rx_lane1_sync_clk";
>>> +			freq-table-hz =
>>> +				<75000000 300000000>,
>>> +				<0 0>,
>>> +				<0 0>,
>>> +				<75000000 300000000>,
>>> +				<0 0>,
>>> +				<0 0>,
>>> +				<0 0>,
>>> +				<0 0>;
>>> +			status = "disabled";
>>> +		};
>>> +
>>> +		ufs_mem_phy: phy@1d87000 {
>>> +			compatible = "qcom,sc7280-qmp-ufs-phy";
>>> +			reg = <0x0 0x01d87000 0x0 0xe00>;
>>> +			clocks = <&rpmhcc RPMH_CXO_CLK>,
>>> +				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
>>> +				 <&gcc GCC_UFS_1_CLKREF_EN>;
>>> +			clock-names = "ref", "ref_aux", "qref";
>>> +
>>> +			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
> 
> Hi Nitin,
> 
>>
>> GCC_UFS_PHY_GDSC is UFS controller GDSC. For sc7280 Phy we don't need this.
> 
> In the current dt-bindings the power-domains property is required.
> 
> Is there another power-domain for the PHY to use, or do we need to
> adjust the bindings to not require power-domains property for ufs phy on
> sc7280?
> 
> Also, with "PHY" in the name, it's interesting that this is not for the
> phy ;)
> 
> Regards
> Luca
> 

Hi Luca,

For sc7280 there is no PHY GDSC and only controller GDSC is there.
Hence, I would suggest to update the binding to reflect that 
power-domains is not a required field.

Regards,
Nitin


>>
>>> +
>>> +			resets = <&ufs_mem_hc 0>;
>>> +			reset-names = "ufsphy";
>>> +
>>> +			#clock-cells = <1>;
>>> +			#phy-cells = <0>;
>>> +
>>> +			status = "disabled";
>>> +		};
>>> +
>>>    		ipa: ipa@1e40000 {
>>>    			compatible = "qcom,sc7280-ipa";
>>>    
>>>
>