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[23.128.96.35]) by mx.google.com with ESMTPS id b3-20020a17090a990300b0028573fb25b9si8374327pjp.135.2023.12.04.13.14.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 04 Dec 2023 13:14:12 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=BVX+jD5U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 995DF805B060; Mon, 4 Dec 2023 13:14:09 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231489AbjLDVNx (ORCPT + 99 others); Mon, 4 Dec 2023 16:13:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37840 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234080AbjLDVNv (ORCPT ); Mon, 4 Dec 2023 16:13:51 -0500 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 718BCC0; Mon, 4 Dec 2023 13:13:57 -0800 (PST) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 3B4LDqqU100622; Mon, 4 Dec 2023 15:13:52 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1701724432; bh=TTtMl6DeAd55+r4FAY8x3IfE1sYnGqdIvgTf5/GgWps=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=BVX+jD5Uhx7hdFwBPW6CVsDfApXFYtXM0Xx1BekXZT6wOfUvwyDTrAQyBiXFbVDGo YdN01lPMSVa6MyZVS2P807lfKEF7pGTMYVDdbZLoz7nNPYpw5nw9JBRE4HenOAoD7Y LwzjkoBNaEQF/2haiqlO4q04ILrvJQdWOtGEa2Jo= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 3B4LDq2m053183 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Dec 2023 15:13:52 -0600 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 4 Dec 2023 15:13:52 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 4 Dec 2023 15:13:52 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 3B4LDpJS004440; Mon, 4 Dec 2023 15:13:51 -0600 From: Nishanth Menon To: Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis CC: Nishanth Menon , , , Subject: Re: [PATCH 1/2] arm64: dts: ti: k3-am65: Enable SDHCI nodes at the board level Date: Mon, 4 Dec 2023 15:13:50 -0600 Message-ID: <170172442057.2631270.18215070503834918216.b4-ty@ti.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20231117163339.89952-1-afd@ti.com> References: <20231117163339.89952-1-afd@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 04 Dec 2023 13:14:09 -0800 (PST) Hi Andrew Davis, On Fri, 17 Nov 2023 10:33:38 -0600, Andrew Davis wrote: > SDHCI nodes defined in the top-level AM65 SoC dtsi files are incomplete > and will not be functional unless they are extended. > > As the attached SD/eMMC is only known about at the board integration level, > these nodes should only be enabled when provided with this information. > > Disable the SDHCI nodes in the dtsi files and only enable the ones that > are actually pinned out on a given board. > > [...] I have applied the following to branch ti-k3-dts-next on [1]. Thank you! [1/2] arm64: dts: ti: k3-am65: Enable SDHCI nodes at the board level commit: 006d93519db2e0eacbaeac20cf9d55a4d842a006 [2/2] arm64: dts: ti: k3-am64: Enable SDHCI nodes at the board level commit: 3b6345e3fcf4c93a79f396121cd0e6f98f04da13 All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent up the chain during the next merge window (or sooner if it is a relevant bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. [1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D