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From:   "Huang, Ying" <ying.huang@intel.com>
To:     Srinivasulu Thanneeru <sthanneeru.opensrc@micron.com>
Cc:     Michal Hocko <mhocko@suse.com>, <aneesh.kumar@linux.ibm.com>,
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Subject: Re: [EXT] Re: [RFC PATCH 0/2] Node migration between memory tiers
In-Reply-To: <1db561a9-6984-418d-9305-a2a5ece93696@micron.com> (Srinivasulu
        Thanneeru's message of "Tue, 5 Dec 2023 01:26:07 +0530")
References: <20231130220422.2033-1-sthanneeru.opensrc@micron.com>
        <ZW3zl2Fke5FtQCv3@tiehlicka>
        <1db561a9-6984-418d-9305-a2a5ece93696@micron.com>
Date:   Tue, 05 Dec 2023 17:12:43 +0800
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Srinivasulu Thanneeru <sthanneeru.opensrc@micron.com> writes:

> On 12/4/2023 9:13 PM, Michal Hocko wrote:
>> CAUTION: EXTERNAL EMAIL. Do not click links or open attachments
>> unless you recognize the sender and were expecting this message.
>> On Fri 01-12-23 03:34:20, sthanneeru.opensrc@micron.com wrote:
>>> From: Srinivasulu Thanneeru <sthanneeru.opensrc@micron.com>
>>>
>>> The memory tiers feature allows nodes with similar memory types
>>> or performance characteristics to be grouped together in a
>>> memory tier. However, there is currently no provision for
>>> moving a node from one tier to another on demand.
>> Could you expand on why this is really needed/necessary? What is the
>> actual usecase?
>
> Hi Michal Hock,
>
> Following two use-cases we have observed.
> 1. It is not accurate to group similar memory types in the same tier,
>    because even similar memory types may have different speed grades.
>
> 2. Some systems boots up with CXL devices and DRAM on the same
> memory-tier, we need a way to move the CXL nodes to the correct tier
> from the user space.

The case 2 reminds me a RFC before as follows,

https://lore.kernel.org/linux-mm/20221027065925.476955-1-ying.huang@intel.com/

The basic idea behind is that do we really need to put NUMA nodes with
different performance metrics in one memory tier?  Are there use cases?
Will we have a system with so many different types of memory?

As in your case, you don't want to put DRAM and CXL memory in one memory
tier.  Do you think we will need to put two types of memory in one
memory tier?

--
Best Regards,
Huang, Ying