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Date:   Tue, 5 Dec 2023 11:10:45 +0100
From:   Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
To:     Yoshinori Sato <ysato@users.sourceforge.jp>
Cc:     linux-sh@vger.kernel.org, Damien Le Moal <dlemoal@kernel.org>,
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        Michael Karcher <kernel@mkarcher.dialup.fu-berlin.de>,
        Sergey Shtylyov <s.shtylyov@omp.ru>,
        Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>,
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Subject: Re: [DO NOT MERGE v5 14/37] clk: Compatible with narrow registers
Message-ID: <20231205101045.tl43oexzbtelcazr@pengutronix.de>
References: <cover.1701768028.git.ysato@users.sourceforge.jp>
 <e27ae1458bd2caabef5423e4ed79fe49813e13b1.1701768028.git.ysato@users.sourceforge.jp>
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Hello,

On Tue, Dec 05, 2023 at 06:45:33PM +0900, Yoshinori Sato wrote:
> @@ -675,13 +681,17 @@ struct clk_div_table {
>   * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses a=
re used
>   *	for the divider register.  Setting this flag makes the register acces=
ses
>   *	big endian.
> + * CLK_DIVIDER_REG_8BIT - by default 32bit register accesses are used for
> + *	the gate register.  Setting this flag makes the register accesses 8bi=
t.
> + * CLK_DIVIDER_REG_16BIT - by default 32bit register accesses are used f=
or
> + *	the gate register.  Setting this flag makes the register accesses 16b=
it.
>   */
>  struct clk_divider {
>  	struct clk_hw	hw;
>  	void __iomem	*reg;
>  	u8		shift;
>  	u8		width;
> -	u8		flags;
> +	u32		flags;
>  	const struct clk_div_table	*table;
>  	spinlock_t	*lock;
>  };

I wonder why .flags was made bigger here. The two new flag values would
still fit into the u8, right?

Best regards
Uwe

--=20
Pengutronix e.K.                           | Uwe Kleine-K=F6nig            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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