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[2620:137:e000::3:2]) by mx.google.com with ESMTPS id s30-20020a63215e000000b005a9debd7854si9231416pgm.828.2023.12.05.04.48.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 04:48:44 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 797FB804814B; Tue, 5 Dec 2023 04:48:42 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345212AbjLEMsP convert rfc822-to-8bit (ORCPT + 99 others); Tue, 5 Dec 2023 07:48:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345119AbjLEMsN (ORCPT ); Tue, 5 Dec 2023 07:48:13 -0500 Received: from mail-oa1-f48.google.com (mail-oa1-f48.google.com [209.85.160.48]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46B2BA1 for ; Tue, 5 Dec 2023 04:48:20 -0800 (PST) Received: by mail-oa1-f48.google.com with SMTP id 586e51a60fabf-1fae54afb66so508719fac.1 for ; Tue, 05 Dec 2023 04:48:20 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1701780499; x=1702385299; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IO2l4IJjU9icOifnYG2PsMFmdqAsQXokH8ukawb7hHk=; b=hw7foyWf+Be0pHOxyI7lfH6ZRsP3jH3O3l+CDCR4C2ZcxwOCvcZFEjxIcYspky2hqr 00xu+nJJ+qjiIMH5DdARpYqOZu4L4TTeVnsqNzRAu/isYmdU6p2VvDv5F7JUzaoEjouY iazv5Jgi5/mHXDY9/Hd5Difo/RF+vBh4cHeZ0d9/7z+LQC3oRSGPl89EmSSO9710/IkO cAlU5M8bROsxWkkmsL/+BuIX228HccV1S1SDzjr+bXNjtZ/IK41LerzgdKyUcdNw8xys uS74pBw806anKgZLhb8+PzXzcVVmpDf9czOPPapUmBHAHEu0+WNqC/VaKZOH6D/0wNSX i4Cw== X-Gm-Message-State: AOJu0YxOPE5C8CnK51UWgeLtf/u4SP8KgeMi0Ty4CDYCafDhwqqNX6E9 2edNN+uH1vN9ihL/Ewru70FUiINss9DupjgiPtw= X-Received: by 2002:a05:6870:4d09:b0:1fb:19d6:8715 with SMTP id pn9-20020a0568704d0900b001fb19d68715mr10579229oab.4.1701780499551; Tue, 05 Dec 2023 04:48:19 -0800 (PST) MIME-Version: 1.0 References: <20231204172849.18753-1-jalliste@amazon.com> In-Reply-To: <20231204172849.18753-1-jalliste@amazon.com> From: "Rafael J. Wysocki" Date: Tue, 5 Dec 2023 13:48:07 +0100 Message-ID: Subject: Re: [PATCH] x86: intel_epb: Add earlyparam option to keep bias at performance To: Jack Allister Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, hpa@zytor.com, rafael@kernel.org, len.brown@intel.com, Paul Durrant , Jue Wang , Usama Arif , x86@kernel.org, Hans de Goede , Peter Zijlstra , "Rafael J. Wysocki" , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.0 required=5.0 tests=MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 05 Dec 2023 04:48:42 -0800 (PST) On Mon, Dec 4, 2023 at 6:30 PM Jack Allister wrote: > > There are certain scenarios where it may be intentional that the EPB was > set at to 0/ENERGY_PERF_BIAS_PERFORMANCE on kernel boot. For example, in > data centers a kexec/live-update of the kernel may be performed regularly. > > Usually this live-update is time critical and defaulting of the bias back > to ENERGY_PERF_BIAS_NORMAL may actually be detrimental to the overall > update time if processors' time to ramp up/boost are affected. > > This patch introduces a kernel command line "intel_epb_keep_performance" > which will leave the EPB at performance if during the restoration code path > it is detected as such. > > Signed-off-by: Jack Allister > Cc: Paul Durrant > Cc: Jue Wang > Cc: Usama Arif > --- > arch/x86/kernel/cpu/intel_epb.c | 19 ++++++++++++++++--- > 1 file changed, 16 insertions(+), 3 deletions(-) > > diff --git a/arch/x86/kernel/cpu/intel_epb.c b/arch/x86/kernel/cpu/intel_epb.c > index e4c3ba91321c..0c7dd092f723 100644 > --- a/arch/x86/kernel/cpu/intel_epb.c > +++ b/arch/x86/kernel/cpu/intel_epb.c > @@ -50,7 +50,8 @@ > * the OS will do that anyway. That sometimes is problematic, as it may cause > * the system battery to drain too fast, for example, so it is better to adjust > * it on CPU bring-up and if the initial EPB value for a given CPU is 0, the > - * kernel changes it to 6 ('normal'). > + * kernel changes it to 6 ('normal'). This however is overridable via > + * intel_epb_keep_performance if required. > */ > > static DEFINE_PER_CPU(u8, saved_epb); > @@ -75,6 +76,8 @@ static u8 energ_perf_values[] = { > [EPB_INDEX_POWERSAVE] = ENERGY_PERF_BIAS_POWERSAVE, > }; > > +static bool intel_epb_keep_performance __read_mostly; > + > static int intel_epb_save(void) > { > u64 epb; > @@ -107,8 +110,12 @@ static void intel_epb_restore(void) > */ > val = epb & EPB_MASK; > if (val == ENERGY_PERF_BIAS_PERFORMANCE) { > - val = energ_perf_values[EPB_INDEX_NORMAL]; > - pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); > + if (!intel_epb_keep_performance) { if (!intel_epb_keep_performance && val == ENERGY_PERF_BIAS_PERFORMANCE) { and you need not notify the sysadmin that the original value has returned - they have set the command line switch for this purpose after all. > + val = energ_perf_values[EPB_INDEX_NORMAL]; > + pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n"); > + } else { > + pr_warn_once("ENERGY_PERF_BIAS: Kept at 'performance', no change\n"); > + } > } > } > wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, (epb & ~EPB_MASK) | val); > @@ -213,6 +220,12 @@ static const struct x86_cpu_id intel_epb_normal[] = { > {} > }; > > +static __init int intel_epb_keep_performance_setup(char *str) > +{ > + return kstrtobool(str, &intel_epb_keep_performance); > +} > +early_param("intel_epb_keep_performance", intel_epb_keep_performance_setup); > + > static __init int intel_epb_init(void) > { > const struct x86_cpu_id *id = x86_match_cpu(intel_epb_normal); > -- > 2.40.1 >