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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id h187-20020a636cc4000000b005c688ff3462si3940876pgc.585.2023.12.05.10.43.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 10:43:46 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 6D35681EA5FE; Tue, 5 Dec 2023 10:43:44 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231136AbjLESnR (ORCPT + 99 others); Tue, 5 Dec 2023 13:43:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229483AbjLESnP (ORCPT ); Tue, 5 Dec 2023 13:43:15 -0500 X-Greylist: delayed 1222 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 05 Dec 2023 10:43:22 PST Received: from finn.localdomain (finn.gateworks.com [108.161.129.64]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4636410D3; Tue, 5 Dec 2023 10:43:22 -0800 (PST) Received: from 068-189-091-139.biz.spectrum.com ([68.189.91.139] helo=tharvey.pdc.gateworks.com) by finn.localdomain with esmtp (Exim 4.93) (envelope-from ) id 1rAa4A-00BDe6-Vq; Tue, 05 Dec 2023 18:22:43 +0000 From: Tim Harvey To: Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tim Harvey Subject: [PATCH] arm64: dts: imx8mm-venice-gw7: Fix pci sub-nodes Date: Tue, 5 Dec 2023 10:22:41 -0800 Message-Id: <20231205182241.2550284-1-tharvey@gateworks.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 05 Dec 2023 10:43:44 -0800 (PST) Several schema warnings were fixed in commit d61c5068729a ("arm64: dts: imx8mm-venice-gw7: Fix pci sub-nodes") however the node names and the ethernet NIC node were not quite correct. Fix the node names as the ethernet device should have a node name of 'ethernet' and remove the device_type, #address-cells, #size-cells, and ranges properties that should only be on busses/bridges. Fixes: d61c5068729a ("arm64: dts: imx8mm-venice-gw7: Fix pci sub-nodes") Signed-off-by: Tim Harvey --- .../dts/freescale/imx8mm-venice-gw72xx.dtsi | 18 +++++++----------- .../dts/freescale/imx8mm-venice-gw73xx.dtsi | 18 +++++++----------- .../dts/freescale/imx8mm-venice-gw7902.dts | 10 +++------- 3 files changed, 17 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index a337e8f20441..31f16f7cf37c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -157,33 +157,29 @@ &pcie0 { <&clk IMX8MM_SYS_PLL2_250M>; status = "okay"; - pcie@0,0 { - reg = <0x0000 0 0 0 0>; + pcie@0 { device_type = "pci"; + reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; ranges; - pcie@0,0 { - reg = <0x0000 0 0 0 0>; + pcie@0 { device_type = "pci"; + reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; ranges; - pcie@3,0 { - reg = <0x1800 0 0 0 0>; + pcie@3 { device_type = "pci"; + reg = <0x1800 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; ranges; - eth1: pcie@0,0 { + eth1: ethernet@0 { reg = <0x0000 0 0 0 0>; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - ranges; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 2247d1c4e2af..6f5a6d91c95e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -177,33 +177,29 @@ &pcie0 { <&clk IMX8MM_SYS_PLL2_250M>; status = "okay"; - pcie@0,0 { - reg = <0x0000 0 0 0 0>; + pcie@0 { device_type = "pci"; + reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; ranges; - pcie@0,0 { - reg = <0x0000 0 0 0 0>; + pcie@0 { device_type = "pci"; + reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; ranges; - pcie@4,0 { - reg = <0x2000 0 0 0 0>; + pcie@4 { device_type = "pci"; + reg = <0x2000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; ranges; - eth1: pcie@0,0 { + eth1: ethernet@0 { reg = <0x0000 0 0 0 0>; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - ranges; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 7ef17c2b0e9d..4bb22fdc5d2e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -633,19 +633,15 @@ &pcie0 { <&clk IMX8MM_SYS_PLL2_250M>; status = "okay"; - pcie@0,0 { - reg = <0x0000 0 0 0 0>; + pcie@0 { device_type = "pci"; + reg = <0x0000 0 0 0 0>; #address-cells = <3>; #size-cells = <2>; ranges; - eth1: pcie@0,0 { + eth1: ethernet@0 { reg = <0x0000 0 0 0 0>; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - ranges; local-mac-address = [00 00 00 00 00 00]; }; -- 2.25.1