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[23.128.96.37]) by mx.google.com with ESMTPS id m7-20020a6562c7000000b0056569ee3ae6si9921467pgv.798.2023.12.05.13.53.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 05 Dec 2023 13:53:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id BAB2380B8E5F; Tue, 5 Dec 2023 13:53:55 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230162AbjLEVxp (ORCPT + 99 others); Tue, 5 Dec 2023 16:53:45 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229591AbjLEVxo (ORCPT ); Tue, 5 Dec 2023 16:53:44 -0500 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E84E8C3; Tue, 5 Dec 2023 13:53:50 -0800 (PST) X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="460453461" X-IronPort-AV: E=Sophos;i="6.04,253,1695711600"; d="scan'208";a="460453461" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2023 13:53:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10915"; a="841615284" X-IronPort-AV: E=Sophos;i="6.04,253,1695711600"; d="scan'208";a="841615284" Received: from smile.fi.intel.com ([10.237.72.54]) by fmsmga004.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2023 13:53:41 -0800 Received: from andy by smile.fi.intel.com with local (Exim 4.97) (envelope-from ) id 1rAdMJ-00000002Bv4-03UG; Tue, 05 Dec 2023 23:53:39 +0200 Date: Tue, 5 Dec 2023 23:53:38 +0200 From: Andy Shevchenko To: Nick Desaulniers Cc: Andrew Morton , tanzirh@google.com, Kees Cook , linux-hardening@vger.kernel.org, linux-kernel@vger.kernel.org, Nick DeSaulniers , llvm@lists.linux.dev Subject: Re: [PATCH] lib/string: shrink lib/string.i via IWYU Message-ID: References: <20231205-libstringheader-v1-1-7f9c573053a7@gmail.com> <20231205130449.8e330a26ecbed1f7b5ad5d7a@linux-foundation.org> <20231205132452.418722bea8f6878dca88142a@linux-foundation.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_SOFTFAIL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 05 Dec 2023 13:53:56 -0800 (PST) On Tue, Dec 05, 2023 at 01:39:47PM -0800, Nick Desaulniers wrote: > On Tue, Dec 5, 2023 at 1:24 PM Andrew Morton wrote: > > On Tue, 5 Dec 2023 13:14:16 -0800 Nick Desaulniers wrote: > > > > The preferred way to import bit-fiddling stuff is to include > > > > . Under the hood this may include asm/bitsperlong.h. Or > > > > it may not, depending on Kconfig settings (particularly architecture). > > > > > > Just triple checking my understanding; it looks like > > > include/linux/bits.h unconditionally includes asm/bitsperlong.h (which > > > is implemented per arch) most of which seem to include > > > asm-generic/bitsperlong.h. > > > > > > include/linux/bits.h also defines a few macros (BIT_MASK, BIT_WORD, > > > BITS_PER_BYTE, GENMASK, etc). If lib/string.c is not using any of > > > those, why can't we go straight to #including asm/bitsperlong.h? That > > > should resolve to the arch specific impl which may include > > > asm-generic/bitsperlong.h? > > > > It's just a general rule. If the higher-level include is present, use > > that. Because of the above, plus I guess things might change in the > > future. > > Hmm...how does one know that linux/bits.h is the higher-level include > of asm/bitsperlong.h? > > Do we mention these conventions anywhere under Documentation? Unfortunately it comes with an experience. The problem here is the absence of Documentation for the headers that guarantee inclusion of other headers. In general linux/* are preferred over asm/* but sometimes things are complicated (when some asm ones include linux ones via architectural code and circling around). > > We've been getting better about irregular asm/include files. > > > > But bits.h is a poor example. A better case to study is spinlock.h. > > If this tool recommended including asm/spinlock.h then that won't work > > on any architecture which doesn't implement SMP (there is no > > arch/nios2/include/asm/spinlock.h). > > The tooling Tanzir is working on does wrap IWYU, and does support such > mapping (of 'low level' to 'high level' headers; more so, if it > recommends X you can override to suggest Y instead). > > arch/nios/ also doesn't provide a bug.h, which this patch is > suggesting we include directly. I guess the same goes for > asm/rwonce.h. Have you checked Ingo Molnar's gigantic series (2k+ patches) for the header hell clean up? Perhaps we need to apply that first. -- With Best Regards, Andy Shevchenko