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From:   "Luck, Tony" <tony.luck@intel.com>
To:     "Zhuo, Qiuxu" <qiuxu.zhuo@intel.com>
CC:     Borislav Petkov <bp@alien8.de>, Aristeu Rozanski <aris@redhat.com>,
        "Mauro Carvalho Chehab" <mchehab@kernel.org>,
        "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 0/5] EDAC/igen6: Add EDAC support for several Intel SoCs
 with IBECC
Thread-Topic: [PATCH 0/5] EDAC/igen6: Add EDAC support for several Intel SoCs
 with IBECC
Thread-Index: AQHaFg79xlMaldO9dEGBYjF4lzIXLLCbeH7Q
Date:   Tue, 5 Dec 2023 23:25:52 +0000
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References: <20231113085318.26783-1-qiuxu.zhuo@intel.com>
In-Reply-To: <20231113085318.26783-1-qiuxu.zhuo@intel.com>
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> As these SoCs share similar IBECC registers, most of them are having
> compute die IDs added for EDAC support. There are some minor differences
> among them regarding IBECC presence detection, the number of memory
> controllers, and the most significant bit of the error address.

Applied series.  Thanks.

-Tony