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[2620:137:e000::3:6]) by mx.google.com with ESMTPS id r5-20020a632b05000000b005c670f98a72si6353141pgr.116.2023.12.06.06.21.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 06:21:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id A361981B17D1; Wed, 6 Dec 2023 06:21:01 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378885AbjLFOUb convert rfc822-to-8bit (ORCPT + 99 others); Wed, 6 Dec 2023 09:20:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378884AbjLFOUa (ORCPT ); Wed, 6 Dec 2023 09:20:30 -0500 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [IPv6:2a0a:edc0:2:b01:1d::104]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01E51D4D for ; Wed, 6 Dec 2023 06:20:36 -0800 (PST) Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1rAslC-0004bH-8A; Wed, 06 Dec 2023 15:20:22 +0100 Received: from [2a0a:edc0:0:900:1d::4e] (helo=lupine) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1rAslA-00Dyy8-Sk; Wed, 06 Dec 2023 15:20:20 +0100 Received: from pza by lupine with local (Exim 4.96) (envelope-from ) id 1rAslA-000E1j-2e; Wed, 06 Dec 2023 15:20:20 +0100 Message-ID: Subject: Re: [PATCH v5 4/5] clk: stm32: introduce clocks for STM32MP257 platform From: Philipp Zabel To: gabriel.fernandez@foss.st.com, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Date: Wed, 06 Dec 2023 15:20:20 +0100 In-Reply-To: <20231206140029.492906-5-gabriel.fernandez@foss.st.com> References: <20231206140029.492906-1-gabriel.fernandez@foss.st.com> <20231206140029.492906-5-gabriel.fernandez@foss.st.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT User-Agent: Evolution 3.46.4-2 MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 06 Dec 2023 06:21:01 -0800 (PST) Hi Gabriel, On Mi, 2023-12-06 at 15:00 +0100, gabriel.fernandez@foss.st.com wrote: > From: Gabriel Fernandez > > This driver is intended for the STM32MP25 clock family and utilizes > the stm32-core API, similar to the stm32mp13 clock driver. > > Signed-off-by: Gabriel Fernandez > --- [...] > diff --git a/drivers/clk/stm32/stm32mp25_rcc.h b/drivers/clk/stm32/stm32mp25_rcc.h > new file mode 100644 > index 000000000000..b1aca78a0b22 > --- /dev/null > +++ b/drivers/clk/stm32/stm32mp25_rcc.h > @@ -0,0 +1,4977 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved > + * Author: Gabriel Fernandez for STMicroelectronics. > + */ > + > +#ifndef STM32MP25_RCC_H > +#define STM32MP25_RCC_H > + > +#define RCC_SECCFGR0 0x0 [...] What is the purpose of all the unused #defines? I initially wanted to point out that the _SHIFT #defines are redundant because the same information is already contained in the corresponding _MASK #defines, but it seems like neither of the register field definitions are used anywhere. It appears only some of the *CFGR register offset #defines are actually used. regards Philipp