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Wed, 06 Dec 2023 09:09:30 -0800 (PST) Date: Wed, 06 Dec 2023 09:09:30 -0800 (PST) X-Google-Original-Date: Wed, 06 Dec 2023 09:09:28 PST (-0800) Subject: Re: [PATCH v2 1/8] riscv: errata: Add StarFive JH7100 errata In-Reply-To: <20231130151932.729708-2-emil.renner.berthing@canonical.com> CC: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Paul Walmsley , kernel@esmil.dk, Conor Dooley , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, cristian.ciocaltea@collabora.com, geert@linux-m68k.org, Conor Dooley From: Palmer Dabbelt To: emil.renner.berthing@canonical.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 06 Dec 2023 09:09:43 -0800 (PST) On Thu, 30 Nov 2023 07:19:25 PST (-0800), emil.renner.berthing@canonical.com wrote: > This not really an errata, but since the JH7100 was made before > the standard Zicbom extension it needs the DMA_GLOBAL_POOL and > RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly. > > Acked-by: Conor Dooley > Signed-off-by: Emil Renner Berthing > --- > arch/riscv/Kconfig.errata | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata > index e2c731cfed8c..692de149141f 100644 > --- a/arch/riscv/Kconfig.errata > +++ b/arch/riscv/Kconfig.errata > @@ -53,6 +53,23 @@ config ERRATA_SIFIVE_CIP_1200 > > If you don't know what to do here, say "Y". > > +config ERRATA_STARFIVE_JH7100 > + bool "StarFive JH7100 support" > + depends on ARCH_STARFIVE && NONPORTABLE > + select DMA_GLOBAL_POOL > + select RISCV_DMA_NONCOHERENT > + select RISCV_NONSTANDARD_CACHE_OPS > + select SIFIVE_CCACHE > + default n > + help > + The StarFive JH7100 was a test chip for the JH7110 and has > + caches that are non-coherent with respect to peripheral DMAs. > + It was designed before the Zicbom extension so needs non-standard > + cache operations through the SiFive cache controller. > + > + Say "Y" if you want to support the BeagleV Starlight and/or > + StarFive VisionFive V1 boards. > + > config ERRATA_THEAD > bool "T-HEAD errata" > depends on RISCV_ALTERNATIVE Reviewed-by: Palmer Dabbelt Acked-by: Palmer Dabbelt Thanks for dealing with this. This is mostly DT stuff so I'm fine with it going via Conor's tree, but LMK if you guys want me to take it.