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Wed, 06 Dec 2023 21:46:52 -0800 (PST) Received: from snowbird ([136.25.84.107]) by smtp.gmail.com with ESMTPSA id x5-20020a170902ea8500b001d08e080042sm431944plb.43.2023.12.06.21.46.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 Dec 2023 21:46:51 -0800 (PST) Date: Wed, 6 Dec 2023 21:46:48 -0800 From: Dennis Zhou To: Tejun Heo , Alexandre Ghiti Cc: Alexandre Ghiti , Paul Walmsley , Palmer Dabbelt , Albert Ou , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Dmitry Vyukov , Vincenzo Frascino , Arnd Bergmann , Christoph Lameter , Andrew Morton , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kasan-dev@googlegroups.com, linux-arch@vger.kernel.org, linux-mm@kvack.org Subject: Re: [PATCH 0/2] riscv: Enable percpu page first chunk allocator Message-ID: References: <20231110140721.114235-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Spam-Status: No, score=-1.0 required=5.0 tests=MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 06 Dec 2023 21:47:05 -0800 (PST) Hello, On Wed, Dec 06, 2023 at 09:00:27AM -1000, Tejun Heo wrote: > On Wed, Dec 06, 2023 at 11:08:20AM +0100, Alexandre Ghiti wrote: > > Hi Tejun, > > > > On 10/11/2023 15:07, Alexandre Ghiti wrote: > > > While working with pcpu variables, I noticed that riscv did not support > > > first chunk allocation in the vmalloc area which may be needed as a fallback > > > in case of a sparse NUMA configuration. > > > > > > patch 1 starts by introducing a new function flush_cache_vmap_early() which > > > is needed since a new vmalloc mapping is established and directly accessed: > > > on riscv, this would likely fail in case of a reordered access or if the > > > uarch caches invalid entries in TLB. > > > > > > patch 2 simply enables the page percpu first chunk allocator in riscv. > > > > > > Alexandre Ghiti (2): > > > mm: Introduce flush_cache_vmap_early() and its riscv implementation > > > riscv: Enable pcpu page first chunk allocator > > > > > > arch/riscv/Kconfig | 2 ++ > > > arch/riscv/include/asm/cacheflush.h | 3 ++- > > > arch/riscv/include/asm/tlbflush.h | 2 ++ > > > arch/riscv/mm/kasan_init.c | 8 ++++++++ > > > arch/riscv/mm/tlbflush.c | 5 +++++ > > > include/asm-generic/cacheflush.h | 6 ++++++ > > > mm/percpu.c | 8 +------- > > > 7 files changed, 26 insertions(+), 8 deletions(-) > > > > > > > Any feedback regarding this? > > On cursory look, it looked fine to me but Dennis is maintaining the percpu > tree now. Dennis? > Ah I wasn't sure at the time if we needed this to go through percpu vs risc v. I need to poke tglx and potentially pull some more stuff so I can take it. I regrettably got both the covid and flu vaccines today and feel like a truck hit me. I'll review this tomorrow and make sure it's taken care of for the next merge window. Thanks, Dennis > Thanks. > > -- > tejun