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Thu, 07 Dec 2023 08:27:52 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3B78RpE1001291 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 7 Dec 2023 08:27:51 GMT Received: from [10.218.45.181] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 7 Dec 2023 00:27:47 -0800 Message-ID: <518ad165-7250-4be5-cf1b-ced8aebfcd84@quicinc.com> Date: Thu, 7 Dec 2023 13:57:44 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.3.2 Subject: Re: [PATCH 08/13] scsi: ufs: qcom: Check the return value of ufs_qcom_power_up_sequence() Content-Language: en-US To: Manivannan Sadhasivam , , CC: , , , , , References: <20231201151417.65500-1-manivannan.sadhasivam@linaro.org> <20231201151417.65500-9-manivannan.sadhasivam@linaro.org> From: Nitin Rawat In-Reply-To: <20231201151417.65500-9-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; 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Thu, 07 Dec 2023 00:28:20 -0800 (PST) On 12/1/2023 8:44 PM, Manivannan Sadhasivam wrote: > If ufs_qcom_power_up_sequence() fails, then it makes no sense to enable > the lane clocks and continue ufshcd_hba_enable(). So let's check the return > value of ufs_qcom_power_up_sequence(). > > Signed-off-by: Manivannan Sadhasivam > --- > drivers/ufs/host/ufs-qcom.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c > index 4948dd732aae..e4dd3777a4d4 100644 > --- a/drivers/ufs/host/ufs-qcom.c > +++ b/drivers/ufs/host/ufs-qcom.c > @@ -415,7 +415,10 @@ static int ufs_qcom_hce_enable_notify(struct ufs_hba *hba, > > switch (status) { > case PRE_CHANGE: > - ufs_qcom_power_up_sequence(hba); > + err = ufs_qcom_power_up_sequence(hba); > + if (err) > + return err; > + > /* > * The PHY PLL output is the source of tx/rx lane symbol > * clocks, hence, enable the lane clocks only after PHY Reviewed-by: Nitin Rawat