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Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by DBAPR04MB7286.eurprd04.prod.outlook.com (2603:10a6:10:1aa::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7068.26; Thu, 7 Dec 2023 09:29:31 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::ff06:bbb2:c068:5fb3]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::ff06:bbb2:c068:5fb3%7]) with mapi id 15.20.7046.015; Thu, 7 Dec 2023 09:29:31 +0000 From: "Peng Fan (OSS)" To: sudeep.holla@arm.com, cristian.marussi@arm.com, mturquette@baylibre.com, sboyd@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, ranjani.vaidyanathan@nxp.com, glen.wienecke@nxp.com, nitin.garg_3@nxp.com, chuck.cannon@nxp.com, Peng Fan Subject: [PATCH V2 2/2] clk: scmi: support state_ctrl_forbidden Date: Thu, 7 Dec 2023 17:33:45 +0800 Message-Id: <20231207093345.581048-2-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20231207093345.581048-1-peng.fan@oss.nxp.com> References: <20231207093345.581048-1-peng.fan@oss.nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SG2PR04CA0191.apcprd04.prod.outlook.com (2603:1096:4:14::29) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|DBAPR04MB7286:EE_ X-MS-Office365-Filtering-Correlation-Id: 46838e3a-0833-465a-fb42-08dbf70703a2 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Thu, 07 Dec 2023 01:30:38 -0800 (PST) From: Peng Fan Some clocks may exported to linux, while those clocks are not allowed to configure by Linux. For example: SYS_CLK1----- \ --MUX--->MMC1_CLK / SYS_CLK2----- MMC1 needs set parent, so SYS_CLK1 and SYS_CLK2 are exported to Linux, then the clk propagation will touch SYS_CLK1 or SYS_CLK2. So we need bypass the failure for SYS_CLK1 or SYS_CLK2 when enable the clock of MMC1. Signed-off-by: Peng Fan --- V2: New. Take Cristian's suggestion drivers/clk/clk-scmi.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c index 8cbe24789c24..1d809813eabd 100644 --- a/drivers/clk/clk-scmi.c +++ b/drivers/clk/clk-scmi.c @@ -119,8 +119,14 @@ static int scmi_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *r static int scmi_clk_enable(struct clk_hw *hw) { struct scmi_clk *clk = to_scmi_clk(hw); + int ret; + + ret = scmi_proto_clk_ops->enable(clk->ph, clk->id, NOT_ATOMIC); - return scmi_proto_clk_ops->enable(clk->ph, clk->id, NOT_ATOMIC); + if (ret == -EACCES && clk->info->state_ctrl_forbidden) + return 0; + + return ret; } static void scmi_clk_disable(struct clk_hw *hw) -- 2.37.1