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[23.128.96.37]) by mx.google.com with ESMTPS id f7-20020a170902684700b001cfb84c92fasi1281979pln.70.2023.12.07.06.50.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Dec 2023 06:50:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=bqx8dsk+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id F28E9805ECC8; Thu, 7 Dec 2023 06:50:25 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1443420AbjLGOuO (ORCPT + 99 others); Thu, 7 Dec 2023 09:50:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1443322AbjLGOuM (ORCPT ); Thu, 7 Dec 2023 09:50:12 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB2E4AC for ; Thu, 7 Dec 2023 06:50:18 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DE229C433C7; Thu, 7 Dec 2023 14:50:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701960618; bh=ROv4DFKKEEpLSUSHwElpbfywORQ7vxKS7FhooWQWgrQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=bqx8dsk+Za2R5f1hFZYmCEE/Sr6KkS6eFsETYaOgAs8HGf8d4qq0Db067rEyGEyhs oBhIWAEOUkPpkMYxba0uDwXDsBqalS3CV0N0bMyvX+9yLhvnmeqlbrj8HK7AK00xjU J06J/tliIegHCiPwoyM/37M/haAxsZg5BfKgfpJkLku6PDZOcSIeVs2yMGerEpGy2D Afyghp+yZNbYb1q/itNfMTs13tWtBoFyYOeVHYpWe34GFO4w+ChTNfpEHeDcqgf5mG qCTiHuyaQbJEtAhT2mD0YT5DtG/hKn56Nt7WlSXRter5DFhQEhUE8sp5Svvkj81rcT 9vsdOFnxtKoDw== Date: Thu, 7 Dec 2023 15:50:09 +0100 From: Lorenzo Pieralisi To: Jason Gunthorpe Cc: Catalin Marinas , Marc Zyngier , ankita@nvidia.com, Shameerali Kolothum Thodi , oliver.upton@linux.dev, suzuki.poulose@arm.com, yuzenghui@huawei.com, will@kernel.org, ardb@kernel.org, akpm@linux-foundation.org, gshan@redhat.com, aniketa@nvidia.com, cjia@nvidia.com, kwankhede@nvidia.com, targupta@nvidia.com, vsethi@nvidia.com, acurrid@nvidia.com, apopple@nvidia.com, jhubbard@nvidia.com, danw@nvidia.com, mochs@nvidia.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2 1/1] KVM: arm64: allow the VM to select DEVICE_* and NORMAL_NC for IO memory Message-ID: References: <20231205194822.GL2692119@nvidia.com> <20231206150556.GQ2692119@nvidia.com> <20231206153809.GS2692119@nvidia.com> <20231206164802.GT2692119@nvidia.com> <20231207133825.GI2692119@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231207133825.GI2692119@nvidia.com> X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 07 Dec 2023 06:50:26 -0800 (PST) On Thu, Dec 07, 2023 at 09:38:25AM -0400, Jason Gunthorpe wrote: > On Thu, Dec 07, 2023 at 11:13:52AM +0100, Lorenzo Pieralisi wrote: > > > > What about the other way around - would we have a prefetchable BAR that > > > > has portions which are unprefetchable? > > > > > > I would say possibly. > > > > > > Prefetch is a dead concept in PCIe, it was obsoleted in PCI-X about 20 > > > years ago. No PCIe system has ever done prefetch. > > > > > > There is a strong incentive to mark BAR's as prefetchable because it > > > allows 64 bit addressing in configurations with bridges. > > > > If by strong incentive you mean the "Additional guidance on the > > Prefetchable Bit in Memory Space BARs" in the PCI express specifications, > > I think it has been removed from the spec and the criteria that had to be > > met to implement it were basically impossible to fulfill on ARM systems, > > it did not make any sense in the first place. > > No, I mean many systems don't have room to accommodate large 32 bit > BARs and the only real way to make stuff work is to have a 64 bit BAR > by setting prefetchable. That's what the implementation note I mentioned referred to ;) > Given mis-marking a read-side-effect region as prefetchable has no > actual consequence on PCI-E I would not be surprised to learn people > have done this. PCIe specs 6.1, 7.5.1.2.1 "Base Address Registers" "A function is permitted to mark a range as prefetchable if there are no side effects on reads..." I don't think that an OS should use the prefetchable flag to infer anything (even though we do at the moment -> sysfs mappings, I know that the prefetchable concept is being scrapped from the PCI specs altogether for a reason), I don't see though how we can say that's a SW bug at present given what I quoted above. I'd agree that it is best not to use that flag for new code we are adding (because it will be deprecated soon). Thanks, Lorenzo