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Date:   Fri, 8 Dec 2023 12:33:38 +0100
From:   Miquel Raynal <miquel.raynal@bootlin.com>
To:     Nikita Shubin <nikita.shubin@maquefel.me>
Cc:     Andy Shevchenko <andriy.shevchenko@intel.com>,
        Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Arnd Bergmann <arnd@arndb.de>,
        Linus Walleij <linus.walleij@linaro.org>,
        Neil Armstrong <neil.armstrong@linaro.org>,
        Daniel Golle <daniel@makrotopia.org>,
        Jean Delvare <jdelvare@suse.de>,
        Christophe Kerello <christophe.kerello@foss.st.com>,
        Chris Packham <chris.packham@alliedtelesis.co.nz>,
        Johan Jonker <jbx6244@gmail.com>, linux-kernel@vger.kernel.org,
        linux-mtd@lists.infradead.org,
        Alexander Sverdlin <alexander.sverdlin@gmail.com>
Subject: Re: [PATCH v5 19/39] mtd: rawnand: add support for ts72xx
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        <ZV3y-IJ7JSD3fJeI@smile.fi.intel.com>
        <6bc0cf7ea58fae2e6a3765f673a777788d465984.camel@maquefel.me>
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Hi Nikita,

> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0for (i =3D 0; i < instr->ctx.addr.naddrs; i++)
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0iow=
rite8(instr->ctx.addr.addrs[i], data- =20
> > > >base); =20
> >=20
> > iowrite8_rep() ?
> >  =20
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0case NAND_OP_DATA_IN_INSTR:
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0ioread8_rep(data->base, instr->ctx.data.buf.in,
> > > instr->ctx.data.len); =20
> >=20
> > Hehe, you are even using it...
> >=20
> > ...
> >  =20
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0if (instr->delay_ns) =20
> >=20
> > What will happen if you drop this check?
> >  =20
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0ndelay(instr->delay_ns); =20
>=20
> No idea! I was asked to keep it by Miquel:

Your controller is very simple and just queues whatever command you
ask, precisely when you ask it to do so. But the NAND bus is a bit more
complex and there are minimum delays between certain instructions. This
delay is meant to respect that. Sometimes it will be 0, and sometimes
not. It depends what NAND op you do. You can check the value of these
delays in the core.

Thanks,
Miqu=C3=A8l