Received: by 2002:a05:7412:8d10:b0:f3:1519:9f41 with SMTP id bj16csp2324616rdb; Fri, 8 Dec 2023 05:09:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IFX8lseRW7Pt9aScXPKz94Qrwf1UYpg0ZtJWTUxsZyC3utGH2Lgll7jR4rFczxDc8Fs8a7w X-Received: by 2002:a05:6358:8809:b0:170:7d81:a325 with SMTP id hv9-20020a056358880900b001707d81a325mr3551401rwb.43.1702040995564; Fri, 08 Dec 2023 05:09:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702040995; cv=none; d=google.com; s=arc-20160816; b=wHSBHRwQ0iMYAuEldN4Jx62osmDeIibINYlimkiDBtI0M6jv5PT5pMebirhJWpEKrd hTvNsVurrEmZA5cs4Re9p2rvZ/s27/GY1eEHasEavuZCyCAqb4gZ3xTzG/bLLt92EyNL aPFBakZwkoPflK5jR+rKswh9Sya8jswF3j70YeDFKhaSlZE8RyI5iTLJ7Ahri5iTlpZe Xu9Z8LPXY1+0OdHIGHiqUjJk9gP9YHG638poL4XfZ4d7Iwuss8+XyigYE7rEYcMUfUw4 LbFnAlpErm2QNN5Fag5gEVhgFrubZUDPwrnKxBCWHLdyV9E9i6+Jf9AXOXvDz5E003EO faew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:subject:message-id:date:from:in-reply-to :references:mime-version:dkim-signature; bh=9LGacmcIHoUBXEI5ozVl+HOy1oDLjhGzrBNeMtvAN8A=; fh=x9nihIsdLHjSJ6KRyvsauueqwXneElNuRCT3LM+wRYY=; b=bwGtpbYbHE/xTWbNc0UtucCyy2AYCLVqmoRKVc6LQMngLE6PtnSW5Boq83JsXhW2D8 DzMc5DFLbOM6+0YE4fv//Dj6kubCUUucHHvN7jU2pajuxVprZ2D+FHe/Yi2Zlt1sIvgb cfdD/LD5fR62rkPQBUQUCl9hKhrwIMiUzTiIJJ+pjXtRHDJHk0xoR00FprQ1hGaqfprs DGD9CiD0tupfXAQq9kmE63pLaTAIIlpCieukDpM4EGyV8D0abizFEppjnPxs1XfGZ/BC 3JLMCHeG8EC9QDX/ijMmsS8BpRzV8tmOkuCuE47SVkaohW2DnqE8ek3VcgIjgPFIikSa G8Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LoCAaWSF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id y186-20020a6364c3000000b005c6818b5a24si1523419pgb.245.2023.12.08.05.09.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 05:09:55 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LoCAaWSF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id E9A0B82CB86A; Fri, 8 Dec 2023 05:09:52 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1573787AbjLHNJh (ORCPT + 99 others); Fri, 8 Dec 2023 08:09:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbjLHNJg (ORCPT ); Fri, 8 Dec 2023 08:09:36 -0500 Received: from mail-yb1-xb2a.google.com (mail-yb1-xb2a.google.com [IPv6:2607:f8b0:4864:20::b2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF1A41723 for ; Fri, 8 Dec 2023 05:09:41 -0800 (PST) Received: by mail-yb1-xb2a.google.com with SMTP id 3f1490d57ef6-dbc4df9fb11so859233276.0 for ; Fri, 08 Dec 2023 05:09:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1702040981; x=1702645781; darn=vger.kernel.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=9LGacmcIHoUBXEI5ozVl+HOy1oDLjhGzrBNeMtvAN8A=; b=LoCAaWSF8yLQ9kVM5NCnE/QXwlq1gRd05U5DWPBy0Amit8kFcpgkZhF9VnefvMR/XY fLPThnovmbcpiQ2J5gbx3dcoNRcIGggQ1l3y93A2Fq9r4f7sPQGxex0vKnlb0vcaR0tb OprFVFyz1xPKf73YV8NoRTIJ98FHmSejlfGZ54MAT3mukf+Qcv58ma52tk+xSE1JYQ1v UwSambp5P9cRBkfEBsRpcgVoxp1IvHqQ+4+Z2Ez16buggGVXHYbzJJrFgXod3sAlAXk1 QmOjRJspfCjM/dSlcMJ0o/GRZzyLJjqdkXFy4cmZ8ht8o8g7zDbLf963F2A1nfjpXqbF DSLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702040981; x=1702645781; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9LGacmcIHoUBXEI5ozVl+HOy1oDLjhGzrBNeMtvAN8A=; b=P2y6g2a7beckYI3xyYn5XN27eGrqtw1nGpeBO//GnSxTKIWYFBJXHT1j+yw6fkN1sQ 0QRCZalK6YgbP/tCOcHAryj4Kf669DiXzsDU6cH1e9HTL+blibROz4bhjzi6JEMZ41Fv OfYC/6sbwOWA1BxliLCBE13GZTg/dfROb/fWL2q7AiUnbKJWzDuDFduaIxYLfeFDuYBB tyiFIHvAqVAzGlWU+EkKFIwigpI5fEXDLLlxeltpuWv64T9YnVRJwvJu1WFbg5Pvl+4D NrKZXTxgwLNJxQ+SuKw6hwjyvAZtEdNY0ykHtWMYF4IdUXCpXCNRJwvcFMtso4Ib53Q4 kaUw== X-Gm-Message-State: AOJu0Yy+G6acJVKcgGKShsip9nyaBGtxU9UVk1S1Y/HnEBezh0tbYfo1 apIw2xLGYkMxOYBXIkzJ3tZL6vKzy/0bovgha+FenA== X-Received: by 2002:a25:381:0:b0:d9a:dfd2:cce3 with SMTP id 123-20020a250381000000b00d9adfd2cce3mr3650992ybd.58.1702040980913; Fri, 08 Dec 2023 05:09:40 -0800 (PST) MIME-Version: 1.0 References: <20231122-phy-qualcomm-edp-x1e80100-v3-0-576fc4e9559d@linaro.org> <20231122-phy-qualcomm-edp-x1e80100-v3-2-576fc4e9559d@linaro.org> <545d3ace-66e5-4470-b3a4-cbdac5ae473d@linaro.org> <29d7c97f-cc98-4f67-9bdc-3005796180c9@linaro.org> In-Reply-To: <29d7c97f-cc98-4f67-9bdc-3005796180c9@linaro.org> From: Dmitry Baryshkov Date: Fri, 8 Dec 2023 15:09:29 +0200 Message-ID: Subject: Re: [PATCH v3 2/3] dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles To: Krzysztof Kozlowski Cc: Konrad Dybcio , Abel Vesa , Andy Gross , Bjorn Andersson , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abhinav Kumar , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Fri, 08 Dec 2023 05:09:53 -0800 (PST) On Fri, 8 Dec 2023 at 14:47, Krzysztof Kozlowski wrote: > > On 08/12/2023 13:35, Dmitry Baryshkov wrote: > >>>>> Same applies to the displayport-controller. It can either drive the DP > >>>>> or eDP output, hardware-wise it is the same. > >>>> > >>>> Therefore what I proposed was correct - the block which uses the phy > >>>> configures its mode. Because this part: > >>>> "this phy is of this type on this board". > >>>> is not true. The phy is both types. > >>> > >>> But hopefully you don't mean using #phy-cells here. There are no > >>> sub-PHYs or anything like that. > >> > >> I am exactly talking about phy-cells. Look at first example from Abel's > >> code. > > > > I always had an impression that #foo-cells means that there are > > different units within the major handler. I.e. #clock-cells mean that > > there are several different clocks, #reset-cells mean that there are > > several resets, etc. > > Ok, maybe this is not a perfect description. We need cells to identify > > a particular instance within the major block. Maybe that sounds more > > correct. > > No, the cells have also meaning of additional arguments. See usage of > phy-type (not the one here, but the correct one) and PWMs. phy-type being used for the 7nm DSI PHY, where it specify exactly the same thing: whether the connected device uses D-PHY or C-PHY modes of the PHY. cdns,phy-type - selecs between PCIe, DP, USB3 or other modes of the PHY ti/emif.txt: phy-type specifies which PHY is attached / used in the controller xlnx,phy-type: deprecated in favour of phy-mode, selects MII mode for the PHY marvell,xenon-phy-type: I _think_ this specifies the actual PHY attached to the controller in hardware. > > For the USB+DP PHY we use #phy-cells to select between USB3 and DP > > PHYs. But for these PHYs we do not have sub-devices, sub-blocks, etc. > > There is a single PHY which works in either of the modes. > > Is it different than case here? Hmm, I was not clear enough. USB+DP = two different PHYs in the same hardware block. DP-eDP = single PHY, working in one of the modes. > > > > > Last, but not least, using #phy-cells in this way would create > > asymmetry with all the other PHYs (and especially other QMP PHYs) > > present on these platforms. > > OK. Is phy-type not something different? No. It doesn't redefine what we already have for other QMP PHYs, it defines new property. > > > > > If you feel that phy-type is not an appropriate solution, I'd vote for > > not having the type in DT at all, letting the DP controller determine > > the proper mode on its own. > > Can we do it? That's BTW the best option. That's a good question. We have separate -dp and -edp compatibles for the DP controller, but I think those also should go, at least for newer platforms. And the reason is the same, there is a single hardware block, just two modes of operation. See mdss_dp3 in the X13s's DT file. I had a thought of using aux-bus presence to determine whether the controller is working in the DP or eDP modes. But this might need additional care for older DT files. -- With best wishes Dmitry