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From:   Thomas Gleixner <tglx@linutronix.de>
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Subject: Re: [PATCH v4 02/13] irqchip/riscv-intc: Allow large non-standard
 interrupt number
In-Reply-To: <20231122121235.827122-3-peterlin@andestech.com>
References: <20231122121235.827122-1-peterlin@andestech.com>
 <20231122121235.827122-3-peterlin@andestech.com>
Date:   Fri, 08 Dec 2023 16:54:34 +0100
Message-ID: <871qbwsn9h.ffs@tglx>
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On Wed, Nov 22 2023 at 20:12, Yu Chien Peter Lin wrote:
> Currently, the implementation of the RISC-V INTC driver uses the
> interrupt cause as hwirq and has a limitation of supporting a

s/hwirq/hardware interrupt/

Please spell things out. We are not on Xitter here.

> maximum of 64 hwirqs. However, according to the privileged spec,
> interrupt causes >= 16 are defined for platform use.
>
> This limitation prevents us from fully utilizing the available

This limitation prevents to fully utilize the ... 

> local interrupt sources. Additionally, the hwirqs used on RISC-V
> are sparse, with only interrupt numbers 1, 5 and 9 (plus Sscofpmf
> or T-Head's PMU irq) being currently used for supervisor mode.
>
> Switch to using irq_domain_create_tree() to create the radix tree
> map, so a larger number of hardware interrupts can be handled.