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From:   <Ryan.Wanner@microchip.com>
To:     <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
        <claudiu.beznea@tuxon.dev>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>,
        Ryan Wanner <Ryan.Wanner@microchip.com>
Subject: [PATCH] drivers: soc: atmel: Adjust defines to follow alphabetical order
Date:   Fri, 8 Dec 2023 10:02:30 -0700
Message-ID: <20231208170230.551265-1-Ryan.Wanner@microchip.com>
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From: Ryan Wanner <Ryan.Wanner@microchip.com>

Move the defines so that they are in aphabetical order based on SOC.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
 drivers/soc/atmel/soc.h | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/soc/atmel/soc.h b/drivers/soc/atmel/soc.h
index 26dd26b4f179..9b2d31073b88 100644
--- a/drivers/soc/atmel/soc.h
+++ b/drivers/soc/atmel/soc.h
@@ -39,13 +39,13 @@ at91_soc_init(const struct at91_soc *socs);
 #define AT91SAM9261_CIDR_MATCH		0x019703a0
 #define AT91SAM9263_CIDR_MATCH		0x019607a0
 #define AT91SAM9G20_CIDR_MATCH		0x019905a0
-#define AT91SAM9RL64_CIDR_MATCH		0x019b03a0
 #define AT91SAM9G45_CIDR_MATCH		0x019b05a0
-#define AT91SAM9X5_CIDR_MATCH		0x019a05a0
 #define AT91SAM9N12_CIDR_MATCH		0x019a07a0
+#define AT91SAM9RL64_CIDR_MATCH		0x019b03a0
+#define AT91SAM9X5_CIDR_MATCH		0x019a05a0
 #define SAM9X60_CIDR_MATCH		0x019b35a0
-#define SAMA7G5_CIDR_MATCH		0x00162100
 #define SAM9X7_CIDR_MATCH		0x09750020
+#define SAMA7G5_CIDR_MATCH		0x00162100
 
 #define AT91SAM9M11_EXID_MATCH		0x00000001
 #define AT91SAM9M10_EXID_MATCH		0x00000002
@@ -62,19 +62,15 @@ at91_soc_init(const struct at91_soc *socs);
 #define AT91SAM9N12_EXID_MATCH		0x00000006
 #define AT91SAM9CN11_EXID_MATCH		0x00000009
 
+#define AT91SAM9XE128_CIDR_MATCH	0x329973a0
+#define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
+#define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0
+
 #define SAM9X60_EXID_MATCH		0x00000000
 #define SAM9X60_D5M_EXID_MATCH		0x00000001
 #define SAM9X60_D1G_EXID_MATCH		0x00000010
 #define SAM9X60_D6K_EXID_MATCH		0x00000011
 
-#define SAMA7G51_EXID_MATCH		0x3
-#define SAMA7G52_EXID_MATCH		0x2
-#define SAMA7G53_EXID_MATCH		0x1
-#define SAMA7G54_EXID_MATCH		0x0
-#define SAMA7G54_D1G_EXID_MATCH		0x00000018
-#define SAMA7G54_D2G_EXID_MATCH		0x00000020
-#define SAMA7G54_D4G_EXID_MATCH		0x00000028
-
 #define SAM9X75_EXID_MATCH		0x00000000
 #define SAM9X72_EXID_MATCH		0x00000004
 #define SAM9X70_EXID_MATCH		0x00000005
@@ -83,10 +79,6 @@ at91_soc_init(const struct at91_soc *socs);
 #define SAM9X75_D1M_EXID_MATCH		0x00000003
 #define SAM9X75_D2G_EXID_MATCH		0x00000006
 
-#define AT91SAM9XE128_CIDR_MATCH	0x329973a0
-#define AT91SAM9XE256_CIDR_MATCH	0x329a93a0
-#define AT91SAM9XE512_CIDR_MATCH	0x329aa3a0
-
 #define SAMA5D2_CIDR_MATCH		0x0a5c08c0
 #define SAMA5D21CU_EXID_MATCH		0x0000005a
 #define SAMA5D225C_D1M_EXID_MATCH	0x00000053
@@ -122,6 +114,14 @@ at91_soc_init(const struct at91_soc *socs);
 #define SAMA5D43_EXID_MATCH		0x00000003
 #define SAMA5D44_EXID_MATCH		0x00000004
 
+#define SAMA7G51_EXID_MATCH		0x3
+#define SAMA7G52_EXID_MATCH		0x2
+#define SAMA7G53_EXID_MATCH		0x1
+#define SAMA7G54_EXID_MATCH		0x0
+#define SAMA7G54_D1G_EXID_MATCH		0x00000018
+#define SAMA7G54_D2G_EXID_MATCH		0x00000020
+#define SAMA7G54_D4G_EXID_MATCH		0x00000028
+
 #define SAME70Q21_CIDR_MATCH		0x21020e00
 #define SAME70Q21_EXID_MATCH		0x00000002
 #define SAME70Q20_CIDR_MATCH		0x21020c00
-- 
2.39.2