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Subject: Re: [PATCH v4 09/22] MIPS: traps: Handle CPU with non standard vint
 offset
To:     Gregory CLEMENT <gregory.clement@bootlin.com>,
        Paul Burton <paulburton@kernel.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        <linux-mips@vger.kernel.org>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
CC:     Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>,
        Tawfik Bayouk <tawfik.bayouk@mobileye.com>,
        Alexandre Belloni <alexandre.belloni@bootlin.com>,
        =?UTF-8?Q?Th=c3=a9o_Lebrun?= <theo.lebrun@bootlin.com>,
        Thomas Petazzoni <thomas.petazzoni@bootlin.com>
References: <20231208161249.1827174-1-gregory.clement@bootlin.com>
 <20231208161249.1827174-10-gregory.clement@bootlin.com>
From:   Sergey Shtylyov <s.shtylyov@omp.ru>
Organization: Open Mobile Platform
Message-ID: <94e4bafb-7c4d-d6bf-7440-f487243a1a59@omp.ru>
Date:   Fri, 8 Dec 2023 20:19:48 +0300
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On 12/8/23 7:12 PM, Gregory CLEMENT wrote:

> From: Jiaxun Yang <jiaxun.yang@flygoat.com>
> 
> Some BMIPS cpus has none standard start offset for vector interrupts.
> 
> Handle those CPUs in vector size calculation and handler setup process.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++---------
>  1 file changed, 23 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index ea59d321f713e..651c9ec6265a9 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -74,7 +74,6 @@
>  
>  #include "access-helper.h"
>  
> -#define MAX(a, b) ((a) >= (b) ? (a) : (b))
>  
>  extern void check_wait(void);
>  extern asmlinkage void rollback_handle_int(void);
> @@ -2005,6 +2004,7 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs)
>  unsigned long ebase;
>  EXPORT_SYMBOL_GPL(ebase);
>  unsigned long exception_handlers[32];
> +static unsigned long vi_vecbase;
>  unsigned long vi_handlers[64];
>  
>  void reserve_exception_space(phys_addr_t addr, unsigned long size)
> @@ -2074,7 +2074,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
>  		handler = (unsigned long) addr;
>  	vi_handlers[n] = handler;
>  
> -	b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
> +	b = (unsigned char *)(vi_vecbase + n*VECTORSPACING);

   Add spaces around * for consistency please.

[...]
> @@ -2370,20 +2370,33 @@ void __init trap_init(void)
>  	extern char except_vec3_generic;
>  	extern char except_vec4;
>  	extern char except_vec3_r4000;
> -	unsigned long i, vec_size;
> +	unsigned long i, vec_size, vi_vec_offset;
>  	phys_addr_t ebase_pa;
>  
>  	check_wait();
>  
> +	if (cpu_has_veic || cpu_has_vint) {
> +		switch (current_cpu_type()) {
> +		case CPU_BMIPS3300:
> +		case CPU_BMIPS4380:
> +			vi_vec_offset = 0x400;
> +			break;
> +		case CPU_BMIPS5000:
> +			vi_vec_offset = 0x1000;
> +			break;
> +		default:
> +			vi_vec_offset = 0x200;
> +			break;
> +		}
> +		vec_size = vi_vec_offset + VECTORSPACING*64;

   Here as well...

[...]

MBR, Sergey