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Fri, 08 Dec 2023 09:46:13 -0800 (PST) X-Received: by 2002:a05:620a:24d6:b0:77f:56f7:8a8a with SMTP id m22-20020a05620a24d600b0077f56f78a8amr1178678qkn.20.1702057573706; Fri, 08 Dec 2023 09:46:13 -0800 (PST) Received: from fedora ([2600:1700:1ff0:d0e0::47]) by smtp.gmail.com with ESMTPSA id i19-20020a056214031300b0067aa164861dsm967730qvu.35.2023.12.08.09.46.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 09:46:13 -0800 (PST) Date: Fri, 8 Dec 2023 11:46:11 -0600 From: Andrew Halaney To: Manivannan Sadhasivam Cc: martin.petersen@oracle.com, jejb@linux.ibm.com, andersson@kernel.org, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-scsi@vger.kernel.org, linux-kernel@vger.kernel.org, quic_cang@quicinc.com, quic_nitirawa@quicinc.com Subject: Re: [PATCH v2 14/17] scsi: ufs: qcom: Simplify ufs_qcom_{assert/deassert}_reset Message-ID: References: <20231208065902.11006-1-manivannan.sadhasivam@linaro.org> <20231208065902.11006-15-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231208065902.11006-15-manivannan.sadhasivam@linaro.org> X-Spam-Status: No, score=0.6 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Fri, 08 Dec 2023 09:46:39 -0800 (PST) On Fri, Dec 08, 2023 at 12:28:59PM +0530, Manivannan Sadhasivam wrote: > In both the functions, UFS_PHY_SOFT_RESET contains the mask of the reset > bit. So this can be passed directly as the value to be written for > asserting the reset. For deasserting, 0 can be passed. > > This gets rid of the FIELD_PREP() inside these functions and also > UFS_PHY_RESET_{ENABLE/DISABLE} definitions. > > Signed-off-by: Manivannan Sadhasivam Reviewed-by: Andrew Halaney > --- > drivers/ufs/host/ufs-qcom.h | 9 ++------- > 1 file changed, 2 insertions(+), 7 deletions(-) > > diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h > index 53db424a0bcb..a109d3359db4 100644 > --- a/drivers/ufs/host/ufs-qcom.h > +++ b/drivers/ufs/host/ufs-qcom.h > @@ -92,9 +92,6 @@ enum { > #define TEST_BUS_SEL GENMASK(22, 19) > #define UFS_REG_TEST_BUS_EN BIT(30) > > -#define UFS_PHY_RESET_ENABLE 1 > -#define UFS_PHY_RESET_DISABLE 0 > - > /* bit definitions for REG_UFS_CFG2 register */ > #define UAWM_HW_CGC_EN BIT(0) > #define UARM_HW_CGC_EN BIT(1) > @@ -157,8 +154,7 @@ ufs_qcom_get_controller_revision(struct ufs_hba *hba, > > static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) > { > - ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_ENABLE), > - REG_UFS_CFG1); > + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, UFS_PHY_SOFT_RESET, REG_UFS_CFG1); > > /* > * Make sure assertion of ufs phy reset is written to > @@ -169,8 +165,7 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba) > > static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba) > { > - ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, FIELD_PREP(UFS_PHY_SOFT_RESET, UFS_PHY_RESET_DISABLE), > - REG_UFS_CFG1); > + ufshcd_rmwl(hba, UFS_PHY_SOFT_RESET, 0, REG_UFS_CFG1); > > /* > * Make sure de-assertion of ufs phy reset is written to > -- > 2.25.1 >