Received: by 2002:a05:7412:8d10:b0:f3:1519:9f41 with SMTP id bj16csp4078683rdb; Mon, 11 Dec 2023 08:15:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IH0wnJuvrKKajSNleHeOJLVFzZk7D/7m6E6hvjDbqWv87bA3OP+/MEhgA7Ho/qT1EeJYAFA X-Received: by 2002:a05:6a00:464b:b0:68f:a92a:8509 with SMTP id kp11-20020a056a00464b00b0068fa92a8509mr7247960pfb.7.1702311311661; Mon, 11 Dec 2023 08:15:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1702311311; cv=none; d=google.com; s=arc-20160816; b=lHIImAer6xIhS9hlGUtnQncC61olyja+viWtAzEInFq9aSsl5Qv2DvAAZO7bvOImja AqcLz0cwgDdsKpHZ8cO5drnzAcsDqF/5+5FuH74ZJUkOlk1SJc8qdtMH7G3f+pz4Xmyh Vb9GRyZFfBInDVoDzIikUmkl22ZYoeL1X+J3afs/M816ZdfJTDVYWJML0xfatXeKUvji LgRv9/k+f8cWbrrS3wQM4bCHSna1o9I/EcyD7e6ks8ux24ytO+2b6UDPT5P7gat9rwHG Z1cVmkUP9POVeYqTBDAB/aIwnsf2nDXxYZfcLHS6JHHk4AAs632/HTFkZ3waWWlJG7n4 r4dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=x5X3kS3e3noD+LAq0r0NSHjbBFDgVbIlhy7fIGQha2c=; fh=oRTr1d7mCDMKQCV8DFHHjee6VGmKsUMMuSV4+yK9gas=; b=zHcE22Gq48UEb7vBoS1vOaeGtw9eYWwHyEJcLv//C5NvL8bwT3L37yN9hvMpINwq3r vLEMpS7XbB4LXnDGbUsN4OpHkoGQVY7HNs5IyirYiTssiMkr5b2t4VozsbLIaT/ZbEp5 TMR9qmY1Zhdae9o6xGzrsaQqWyIKrmS70d8y91IWXVPuJpLFy8rYXu7pMcVIzXgqt5Eq pRKHHeNDuNHsr0AhxEScqJXq9JKrkALq2QP2qybwKXrkhWu35NNWD3t/WfyFh47HPnpl XP9kUVfEhBGDCCh7GPjohC/DZDG8MTw3+kbxwPSmGQftkprae6aPS4YPhP08zODOEAUz 5q6w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Return-Path: Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id s42-20020a056a0017aa00b006cec77b95a3si6211646pfg.279.2023.12.11.08.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Dec 2023 08:15:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 81A34807E406; Mon, 11 Dec 2023 08:15:05 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344601AbjLKQOf (ORCPT + 99 others); Mon, 11 Dec 2023 11:14:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344508AbjLKQOX (ORCPT ); Mon, 11 Dec 2023 11:14:23 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 1799010F; Mon, 11 Dec 2023 08:14:30 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5AD1C16A3; Mon, 11 Dec 2023 08:15:16 -0800 (PST) Received: from e127643.broadband (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DBC793F738; Mon, 11 Dec 2023 08:14:25 -0800 (PST) From: James Clark To: linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, suzuki.poulose@arm.com, will@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com Cc: namhyung@gmail.com, James Clark , Catalin Marinas , Jonathan Corbet , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ian Rogers , Adrian Hunter , Russell King , Marc Zyngier , Oliver Upton , James Morse , Zenghui Yu , Paolo Bonzini , Shuah Khan , Zaid Al-Bassam , Raghavendra Rao Ananta , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: [PATCH v7 03/11] arm: perf: Use GENMASK for PMMIR fields Date: Mon, 11 Dec 2023 16:13:15 +0000 Message-Id: <20231211161331.1277825-4-james.clark@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211161331.1277825-1-james.clark@arm.com> References: <20231211161331.1277825-1-james.clark@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Mon, 11 Dec 2023 08:15:06 -0800 (PST) This is so that FIELD_GET and FIELD_PREP can be used and that the fields are in a consistent format to arm64/tools/sysreg Signed-off-by: James Clark --- drivers/perf/arm_pmuv3.c | 8 +++----- include/linux/perf/arm_pmuv3.h | 9 +++------ 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index e424de5dd44f..7b2c1d03464a 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -328,7 +328,7 @@ static ssize_t slots_show(struct device *dev, struct device_attribute *attr, { struct pmu *pmu = dev_get_drvdata(dev); struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); - u32 slots = cpu_pmu->reg_pmmir & ARMV8_PMU_SLOTS_MASK; + u32 slots = FIELD_GET(ARMV8_PMU_SLOTS, cpu_pmu->reg_pmmir); return sysfs_emit(page, "0x%08x\n", slots); } @@ -340,8 +340,7 @@ static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr, { struct pmu *pmu = dev_get_drvdata(dev); struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); - u32 bus_slots = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_SLOTS_SHIFT) - & ARMV8_PMU_BUS_SLOTS_MASK; + u32 bus_slots = FIELD_GET(ARMV8_PMU_BUS_SLOTS, cpu_pmu->reg_pmmir); return sysfs_emit(page, "0x%08x\n", bus_slots); } @@ -353,8 +352,7 @@ static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr, { struct pmu *pmu = dev_get_drvdata(dev); struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu); - u32 bus_width = (cpu_pmu->reg_pmmir >> ARMV8_PMU_BUS_WIDTH_SHIFT) - & ARMV8_PMU_BUS_WIDTH_MASK; + u32 bus_width = FIELD_GET(ARMV8_PMU_BUS_WIDTH, cpu_pmu->reg_pmmir); u32 val = 0; /* Encoded as Log2(number of bytes), plus one */ diff --git a/include/linux/perf/arm_pmuv3.h b/include/linux/perf/arm_pmuv3.h index ed62bd75cec7..1bc7678c10d4 100644 --- a/include/linux/perf/arm_pmuv3.h +++ b/include/linux/perf/arm_pmuv3.h @@ -250,12 +250,9 @@ #define ARMV8_PMU_USERENR_ER (1 << 3) /* Event counter can be read at EL0 */ /* PMMIR_EL1.SLOTS mask */ -#define ARMV8_PMU_SLOTS_MASK 0xff - -#define ARMV8_PMU_BUS_SLOTS_SHIFT 8 -#define ARMV8_PMU_BUS_SLOTS_MASK 0xff -#define ARMV8_PMU_BUS_WIDTH_SHIFT 16 -#define ARMV8_PMU_BUS_WIDTH_MASK 0xf +#define ARMV8_PMU_SLOTS GENMASK(7, 0) +#define ARMV8_PMU_BUS_SLOTS GENMASK(15, 8) +#define ARMV8_PMU_BUS_WIDTH GENMASK(19, 16) /* * This code is really good -- 2.34.1