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From:   "Rafael J. Wysocki" <rafael@kernel.org>
Date:   Mon, 11 Dec 2023 20:59:33 +0100
Message-ID: <CAJZ5v0hJbmzBzf9NdUpDB+qhY_uSVaExi=o=1F7X-Y_V5RRmmA@mail.gmail.com>
Subject: Re: [PATCH] intel_idle: Add Meteorlake support
To:     Zhang Rui <rui.zhang@intel.com>
Cc:     rafael.j.wysocki@intel.com, lenb@kernel.org,
        linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org
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On Fri, Dec 1, 2023 at 7:10 PM Zhang Rui <rui.zhang@intel.com> wrote:
>
> Add intel_idle support for MeteorLake.
>
> C1 and C1E states on Meteorlake are mutually exclusive like Alderlake
> and Raptorlake, but they have little latency difference with measureable
> power difference. Thus always enable "C1E promotion" bit and expose C1E
> only.
>
> Expose C6 because it has less power compared with C1E, and smaller
> latency compared with C8/C10.
>
> Ignore C8 and expose C10 because C8 does not show latency advantage
> compared with C10.
>
> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
> ---
>  drivers/idle/intel_idle.c | 34 ++++++++++++++++++++++++++++++++++
>  1 file changed, 34 insertions(+)
>
> diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
> index dcda0afecfc5..cfd0b24fd7f1 100644
> --- a/drivers/idle/intel_idle.c
> +++ b/drivers/idle/intel_idle.c
> @@ -923,6 +923,35 @@ static struct cpuidle_state adl_l_cstates[] __initdata = {
>                 .enter = NULL }
>  };
>
> +static struct cpuidle_state mtl_l_cstates[] __initdata = {
> +       {
> +               .name = "C1E",
> +               .desc = "MWAIT 0x01",
> +               .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
> +               .exit_latency = 1,
> +               .target_residency = 1,
> +               .enter = &intel_idle,
> +               .enter_s2idle = intel_idle_s2idle, },
> +       {
> +               .name = "C6",
> +               .desc = "MWAIT 0x20",
> +               .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
> +               .exit_latency = 140,
> +               .target_residency = 420,
> +               .enter = &intel_idle,
> +               .enter_s2idle = intel_idle_s2idle, },
> +       {
> +               .name = "C10",
> +               .desc = "MWAIT 0x60",
> +               .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
> +               .exit_latency = 310,
> +               .target_residency = 930,
> +               .enter = &intel_idle,
> +               .enter_s2idle = intel_idle_s2idle, },
> +       {
> +               .enter = NULL }
> +};
> +
>  static struct cpuidle_state gmt_cstates[] __initdata = {
>         {
>                 .name = "C1",
> @@ -1349,6 +1378,10 @@ static const struct idle_cpu idle_cpu_adl_l __initconst = {
>         .state_table = adl_l_cstates,
>  };
>
> +static const struct idle_cpu idle_cpu_mtl_l __initconst = {
> +       .state_table = mtl_l_cstates,
> +};
> +
>  static const struct idle_cpu idle_cpu_gmt __initconst = {
>         .state_table = gmt_cstates,
>  };
> @@ -1423,6 +1456,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = {
>         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,           &idle_cpu_icx),
>         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           &idle_cpu_adl),
>         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         &idle_cpu_adl_l),
> +       X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L,        &idle_cpu_mtl_l),
>         X86_MATCH_INTEL_FAM6_MODEL(ATOM_GRACEMONT,      &idle_cpu_gmt),
>         X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,    &idle_cpu_spr),
>         X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,     &idle_cpu_spr),
> --

Applied as 6.8 material, thanks!