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[23.128.96.36]) by mx.google.com with ESMTPS id t5-20020a6564c5000000b005c65defc409si7670563pgv.748.2023.12.12.07.25.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 07:25:52 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=REAAcd3J; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 137FC808BE6C; Tue, 12 Dec 2023 07:25:48 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376690AbjLLPZG (ORCPT + 99 others); Tue, 12 Dec 2023 10:25:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376671AbjLLPZA (ORCPT ); Tue, 12 Dec 2023 10:25:00 -0500 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C3F8D3; Tue, 12 Dec 2023 07:25:05 -0800 (PST) Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3BCBdgLW003978; Tue, 12 Dec 2023 16:24:09 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=PArOreOCiQOFnjN4DbUh85R/iRgIHuoFoafWk6VLZKU=; b=RE AAcd3Jv5nMdaTUzKKzUJkCwmKyfpCnlq9y9y9k/30bVC76Wwei/P81mkPRJVpjWy V6mscsArS2mWPKaFd8r3y8ih1nHt2fQBhdW4rJ58vb8geDZ+vLVULiRPm3Pla/HE vlv0NNJHMjHgwawAKhliQGEju8mq0BR1zTrlnsB/JQLZENSJyMeGsGdvMqEORRfE h8D2WJwdgBgSUfV/UyJk1aqdGyD3+RysPE1jMM54AI9On3/CdCY9MxFZt5p4X38I YODNdHZ4WXTyT9TAmP17ZqlaCgMrPp4Yb1Mq6Vb2E1PwmZEXZs/WBJfWkMnl6tnO hh5L6pXwMmRMFVWxgjSA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3uw42nhsn1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 12 Dec 2023 16:24:09 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6954010005A; Tue, 12 Dec 2023 16:24:08 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5488822F7B1; Tue, 12 Dec 2023 16:24:08 +0100 (CET) Received: from localhost (10.252.7.20) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Tue, 12 Dec 2023 16:24:07 +0100 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , , , , , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v8 03/13] dt-bindings: bus: document RIFSC Date: Tue, 12 Dec 2023 16:23:46 +0100 Message-ID: <20231212152356.345703-4-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231212152356.345703-1-gatien.chevallier@foss.st.com> References: <20231212152356.345703-1-gatien.chevallier@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.252.7.20] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-12_09,2023-12-12_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 12 Dec 2023 07:25:49 -0800 (PST) Document RIFSC (RIF security controller). RIFSC is a firewall controller composed of different kinds of hardware resources. Signed-off-by: Gatien Chevallier --- Changes in V6: - Renamed access-controller to access-controllers - Removal of access-control-provider property - Removal of access-controller and access-controller-names declaration in the patternProperties field. Add additionalProperties: true in this field. Changes in V5: - Renamed feature-domain* to access-control* Changes in V2: - Corrected errors highlighted by Rob's robot - No longer define the maxItems for the "feature-domains" property - Fix example (node name, status) - Declare "feature-domain-names" as an optional property for child nodes - Fix description of "feature-domains" property .../bindings/bus/st,stm32mp25-rifsc.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml diff --git a/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml new file mode 100644 index 000000000000..95aa7f04c739 --- /dev/null +++ b/Documentation/devicetree/bindings/bus/st,stm32mp25-rifsc.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32 Resource isolation framework security controller + +maintainers: + - Gatien Chevallier + +description: | + Resource isolation framework (RIF) is a comprehensive set of hardware blocks + designed to enforce and manage isolation of STM32 hardware resources like + memory and peripherals. + + The RIFSC (RIF security controller) is composed of three sets of registers, + each managing a specific set of hardware resources: + - RISC registers associated with RISUP logic (resource isolation device unit + for peripherals), assign all non-RIF aware peripherals to zero, one or + any security domains (secure, privilege, compartment). + - RIMC registers: associated with RIMU logic (resource isolation master + unit), assign all non RIF-aware bus master to one security domain by + setting secure, privileged and compartment information on the system bus. + Alternatively, the RISUP logic controlling the device port access to a + peripheral can assign target bus attributes to this peripheral master port + (supported attribute: CID). + - RISC registers associated with RISAL logic (resource isolation device unit + for address space - Lite version), assign address space subregions to one + security domains (secure, privilege, compartment). + +properties: + compatible: + contains: + const: st,stm32mp25-rifsc + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + ranges: true + + "#access-controller-cells": + const: 1 + description: + Contains the firewall ID associated to the peripheral. + +patternProperties: + "^.*@[0-9a-f]+$": + description: Peripherals + type: object + + additionalProperties: true + + required: + - access-controllers + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - "#access-controller-cells" + - ranges + +additionalProperties: false + +examples: + - | + // In this example, the usart2 device refers to rifsc as its domain + // controller. + // Access rights are verified before creating devices. + + #include + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + access-controllers = <&rifsc 32>; + }; + }; -- 2.25.1