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Subject: [PATCH v2 1/2] x86/resctrl: Remove hard-coded memory bandwidth limit
From:   Babu Moger <babu.moger@amd.com>
To:     <corbet@lwn.net>, <fenghua.yu@intel.com>,
        <reinette.chatre@intel.com>, <tglx@linutronix.de>,
        <mingo@redhat.com>, <bp@alien8.de>, <dave.hansen@linux.intel.com>
CC:     <x86@kernel.org>, <hpa@zytor.com>, <paulmck@kernel.org>,
        <rdunlap@infradead.org>, <tj@kernel.org>, <peterz@infradead.org>,
        <seanjc@google.com>, <kim.phillips@amd.com>, <babu.moger@amd.com>,
        <jmattson@google.com>, <ilpo.jarvinen@linux.intel.com>,
        <jithu.joseph@intel.com>, <kan.liang@linux.intel.com>,
        <nikunj@amd.com>, <daniel.sneddon@linux.intel.com>,
        <pbonzini@redhat.com>, <rick.p.edgecombe@intel.com>,
        <rppt@kernel.org>, <maciej.wieczor-retman@intel.com>,
        <linux-doc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <eranian@google.com>, <peternewman@google.com>, <dhagiani@amd.com>,
        <babu.moger@amd.com>
Date:   Tue, 12 Dec 2023 12:02:18 -0600
Message-ID: <170240413801.760665.7930294172146734221.stgit@bmoger-ubuntu>
In-Reply-To: <20231201005720.235639-1-babu.moger@amd.com>
References: <20231201005720.235639-1-babu.moger@amd.com>
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The QOS Memory Bandwidth Enforcement Limit is reported by=0A=
CPUID_Fn80000020_EAX_x01 and CPUID_Fn80000020_EAX_x02.=0A=
Bits Description=0A=
31:0 BW_LEN: Size of the QOS Memory Bandwidth Enforcement Limit.=0A=
=0A=
Newer processors can support higher bandwidth limit than the current=0A=
hard-coded value. Remove the hard-coded value and detect using CPUID=0A=
command. Also update the register variables eax and edx to match the=0A=
AMD CPUID definition.=0A=
=0A=
The CPUID details are documentation in the PPR listed below [1].=0A=
[1] Processor Programming Reference (PPR) Vol 1.1 for AMD Family 19h Model=
=0A=
11h B1 - 55901 Rev 0.25.=0A=
=0A=
Fixes: 4d05bf71f157 ("x86/resctrl: Introduce AMD QOS feature")=0A=
Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537=0A=
Signed-off-by: Babu Moger <babu.moger@amd.com>=0A=
=0A=
---=0A=
v2: Earlier Sent as a part of ABMC feature.=0A=
    https://lore.kernel.org/lkml/20231201005720.235639-1-babu.moger@amd.com=
/=0A=
    Sending it separate now. Addressed comments from Reinette about registe=
rs=0A=
    being used from Intel definition. Also updated commit message.=0A=
---=0A=
 arch/x86/kernel/cpu/resctrl/core.c     |   10 ++++------=0A=
 arch/x86/kernel/cpu/resctrl/internal.h |    1 -=0A=
 2 files changed, 4 insertions(+), 7 deletions(-)=0A=
=0A=
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resct=
rl/core.c=0A=
index 19e0681f0435..d04371e851b4 100644=0A=
--- a/arch/x86/kernel/cpu/resctrl/core.c=0A=
+++ b/arch/x86/kernel/cpu/resctrl/core.c=0A=
@@ -231,9 +231,7 @@ static bool __get_mem_config_intel(struct rdt_resource =
*r)=0A=
 static bool __rdt_get_mem_config_amd(struct rdt_resource *r)=0A=
 {=0A=
 	struct rdt_hw_resource *hw_res =3D resctrl_to_arch_res(r);=0A=
-	union cpuid_0x10_3_eax eax;=0A=
-	union cpuid_0x10_x_edx edx;=0A=
-	u32 ebx, ecx, subleaf;=0A=
+	u32 eax, ebx, ecx, edx, subleaf;=0A=
 =0A=
 	/*=0A=
 	 * Query CPUID_Fn80000020_EDX_x01 for MBA and=0A=
@@ -241,9 +239,9 @@ static bool __rdt_get_mem_config_amd(struct rdt_resourc=
e *r)=0A=
 	 */=0A=
 	subleaf =3D (r->rid =3D=3D RDT_RESOURCE_SMBA) ? 2 :  1;=0A=
 =0A=
-	cpuid_count(0x80000020, subleaf, &eax.full, &ebx, &ecx, &edx.full);=0A=
-	hw_res->num_closid =3D edx.split.cos_max + 1;=0A=
-	r->default_ctrl =3D MAX_MBA_BW_AMD;=0A=
+	cpuid_count(0x80000020, subleaf, &eax, &ebx, &ecx, &edx);=0A=
+	hw_res->num_closid =3D edx + 1;=0A=
+	r->default_ctrl =3D 1 << eax;=0A=
 =0A=
 	/* AMD does not use delay */=0A=
 	r->membw.delay_linear =3D false;=0A=
diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/r=
esctrl/internal.h=0A=
index a4f1aa15f0a2..d2979748fae4 100644=0A=
--- a/arch/x86/kernel/cpu/resctrl/internal.h=0A=
+++ b/arch/x86/kernel/cpu/resctrl/internal.h=0A=
@@ -18,7 +18,6 @@=0A=
 #define MBM_OVERFLOW_INTERVAL		1000=0A=
 #define MAX_MBA_BW			100u=0A=
 #define MBA_IS_LINEAR			0x4=0A=
-#define MAX_MBA_BW_AMD			0x800=0A=
 #define MBM_CNTR_WIDTH_OFFSET_AMD	20=0A=
 =0A=
 #define RMID_VAL_ERROR			BIT_ULL(63)=0A=
=0A=