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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id t9-20020a4a7609000000b0058d76e8ce0dsm2688293ooc.36.2023.12.12.14.54.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Dec 2023 14:54:27 -0800 (PST) Received: (nullmailer pid 2979434 invoked by uid 1000); Tue, 12 Dec 2023 22:54:26 -0000 Date: Tue, 12 Dec 2023 16:54:26 -0600 From: Rob Herring To: Manivannan Sadhasivam Cc: Frank Li , bhelgaas@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, festevam@gmail.com, helgaas@kernel.org, hongxing.zhu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, kw@linux.com, l.stach@pengutronix.de, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org Subject: Re: [PATCH v3 01/13] PCI: imx6: Simplify clock handling by using HAS_CLK_* bitmask Message-ID: <20231212225426.GB2948988-robh@kernel.org> References: <20231211215842.134823-1-Frank.Li@nxp.com> <20231211215842.134823-2-Frank.Li@nxp.com> <20231212164913.GA21240@thinkpad> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231212164913.GA21240@thinkpad> X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 12 Dec 2023 14:54:34 -0800 (PST) On Tue, Dec 12, 2023 at 10:19:13PM +0530, Manivannan Sadhasivam wrote: > On Mon, Dec 11, 2023 at 04:58:30PM -0500, Frank Li wrote: > > Refactors the clock handling logic in the imx6 PCI driver by adding > > HAS_CLK_* bitmask define for drvdata::flags . Simplifies the code and makes > > it more maintainable, as future additions of SOC support will only require > > straightforward changes. The drvdata::flags and a bitmask ensures a cleaner > > and more scalable switch-case structure for handling clocks. > > > > Is there any necessity to validate each clock in the driver? I mean, can't you > just rely on devicetree to provide enough clocks for the functioning of the PCIe > controller? > > If you can rely on devicetree (everyone should in an ideal world), then you can > just use devm_clk_bulk_get_all() to get all available clocks for the SoC and > just enable/disable whatever is available. Or just use the *_get_optional() variants of functions. They return NULL such that subsequent calls are just NOPs if the resource is not present. Of course, they aren't really optional on any given platform in this case, but does that really matter. There isn't an optional variant for phys, but it can be added. > > This will greatly simplify the code. > > Only downside of this approach is, if the devicetree is not supplying enough > clocks, then it will be difficult to find why PCIe is not working. But this also > means that the devicetree is screwed. A sufficient schema should prevent that... That's what they're for, not just torturing people to learn json-schema. :) Rob