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Tue, 12 Dec 2023 21:23:02 -0800 (PST) Date: Wed, 13 Dec 2023 10:52:59 +0530 From: Viresh Kumar To: "xiaowu.ding" Cc: Tushar.Khandelwal@arm.com, jassisinghbrar@gmail.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] mailbox: arm_mhuv2: Fix a bug for mhuv2_sender_interrupt Message-ID: <20231213052259.ug4j7tnmqt3qaxuy@vireshk-i7> References: <20231212113722.863-1-xiaowu.ding@jaguarmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231212113722.863-1-xiaowu.ding@jaguarmicro.com> X-Spam-Status: No, score=4.4 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: **** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 12 Dec 2023 21:23:13 -0800 (PST) On 12-12-23, 19:37, xiaowu.ding wrote: > From: "Xiaowu.ding" > > Message Handling Unit version is v2.1. > > When arm_mhuv2 working with the data protocol transfer mode. > We have split one mhu into two channels, and every channel > include four channel windows, the two channels share > one gic spi interrupt. > > There is a problem with the sending scenario. > > The first channel will take up 0-3 channel windows, and the second > channel take up 4-7 channel windows. When the first channel send the > data, and the receiver will clear all the four channels status. > Although we only enabled the interrupt on the last channel window with > register CH_INT_EN,the register CHCOMB_INT_ST0 will be 0xf, not be 0x8. > Currently we just clear the last channel windows int status with the > data proctol mode.So after that,the CHCOMB_INT_ST0 status will be 0x7, > not be the 0x0. > > Then the second channel send the data, the receiver read the > data, clear all the four channel windows status, trigger the sender > interrupt. But currently the CHCOMB_INT_ST0 register will be 0xf7, > get_irq_chan_comb function will always return the first channel. > > So this patch clear all channel windows int status to avoid this interrupt > confusion. > > Signed-off-by: Xiaowu.ding > --- > drivers/mailbox/arm_mhuv2.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/mailbox/arm_mhuv2.c b/drivers/mailbox/arm_mhuv2.c > index c1ef5016f..15021c90c 100644 > --- a/drivers/mailbox/arm_mhuv2.c > +++ b/drivers/mailbox/arm_mhuv2.c > @@ -553,7 +553,8 @@ static irqreturn_t mhuv2_sender_interrupt(int irq, void *data) > priv = chan->con_priv; > > if (!IS_PROTOCOL_DOORBELL(priv)) { > - writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx + priv->windows - 1].int_clr); > + for (i = 0; i < priv->windows; i++) > + writel_relaxed(1, &mhu->send->ch_wn[priv->ch_wn_idx + i].int_clr); > > if (chan->cl) { > mbox_chan_txdone(chan, 0); Acked-by: Viresh Kumar -- viresh