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Wed, 13 Dec 2023 05:32:16 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BD5WGhi008301 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Dec 2023 05:32:16 GMT Received: from [10.201.3.200] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Tue, 12 Dec 2023 21:32:12 -0800 Message-ID: <51133a78-43ca-46fb-8f5e-b3bfdaef9a79@quicinc.com> Date: Wed, 13 Dec 2023 11:02:09 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/1] hwspinlock: qcom: fix tcsr data for ipq6018 To: Chukun Pan , Bjorn Andersson CC: Andy Gross , Konrad Dybcio , Ohad Ben-Cohen , Baolin Wang , Krzysztof Kozlowski , , , References: <20231212142509.655094-1-amadeus@jmu.edu.cn> Content-Language: en-US From: Vignesh Viswanathan In-Reply-To: <20231212142509.655094-1-amadeus@jmu.edu.cn> Content-Type: text/plain; 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Tue, 12 Dec 2023 21:32:45 -0800 (PST) On 12/12/2023 7:55 PM, Chukun Pan wrote: > The tcsr_mutex hwlock register of the ipq6018 SoC is 0x20000[1], which > should not use the max_register configuration of older SoCs. This will > cause smem to be unable to probe, further causing devices that use > smem-part to parse partitions to fail to boot. > > [ 2.118227] qcom-smem: probe of 4aa00000.memory failed with error -110 > [ 22.273120] platform 79b0000.nand-controller: deferred probe pending > > Remove 'qcom,ipq6018-tcsr-mutex' setting from of_match to fix this. Hi Chukun, This patch was already posted [2] and Bjorn applied the same [3]. Hi Bjorn, This patch is missing in linux-next. Could you please help check ? Thanks, Vignesh [2] https://lore.kernel.org/all/20230905095535.1263113-3-quic_viswanat@quicinc.com/ [3] https://lore.kernel.org/all/169522934567.2501390.1112201061322984444.b4-ty@kernel.org/ > > [1] commit 72fc3d58b87b ("arm64: dts: qcom: ipq6018: Fix tcsr_mutex register size") > Fixes: 5d4753f741d8 ("hwspinlock: qcom: add support for MMIO on older SoCs") > Signed-off-by: Chukun Pan > --- > drivers/hwspinlock/qcom_hwspinlock.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c > index a0fd67fd2934..814dfe8697bf 100644 > --- a/drivers/hwspinlock/qcom_hwspinlock.c > +++ b/drivers/hwspinlock/qcom_hwspinlock.c > @@ -115,7 +115,6 @@ static const struct of_device_id qcom_hwspinlock_of_match[] = { > { .compatible = "qcom,sfpb-mutex", .data = &of_sfpb_mutex }, > { .compatible = "qcom,tcsr-mutex", .data = &of_tcsr_mutex }, > { .compatible = "qcom,apq8084-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, > - { .compatible = "qcom,ipq6018-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, > { .compatible = "qcom,msm8226-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, > { .compatible = "qcom,msm8974-tcsr-mutex", .data = &of_msm8226_tcsr_mutex }, > { .compatible = "qcom,msm8994-tcsr-mutex", .data = &of_msm8226_tcsr_mutex },