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Message-ID: <2b72464e-d60a-6adc-0ef7-ed92ff495859@samsung.com>
Date:   Wed, 13 Dec 2023 17:10:38 +0900
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Subject: Re: [PATCH v4 2/2] pinctrl: samsung: add exynosautov920 pinctrl
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Alim Akhtar <alim.akhtar@samsung.com>,
        Rob Herring <robh+dt@kernel.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Tomasz Figa <tomasz.figa@gmail.com>,
        Sylwester Nawrocki <s.nawrocki@samsung.com>,
        Linus Walleij <linus.walleij@linaro.org>,
        Thierry Reding <thierry.reding@gmail.com>,
        Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jiri Slaby <jirislaby@kernel.org>
Cc:     linux-arm-kernel@lists.infradead.org,
        linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
        linux-pwm@vger.kernel.org, linux-serial@vger.kernel.org
From:   Jaewon Kim <jaewon02.kim@samsung.com>
In-Reply-To: <68a36910-e528-45ff-8b59-e7cd95aaef0b@linaro.org>
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References: <20231211114145.106255-1-jaewon02.kim@samsung.com>
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        <68a36910-e528-45ff-8b59-e7cd95aaef0b@linaro.org>
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On 23. 12. 13. 16:52, Krzysztof Kozlowski wrote:
> On 11/12/2023 12:41, Jaewon Kim wrote:
>> Add pinctrl data for ExynosAutov920 SoC.
>> It has a newly applied pinctrl register layer for ExynosAuto series.
>>
>> Pinctrl data for ExynosAutoV920 SoC.
>>   - GPA0,GPA1 (10): External wake up interrupt
>>   - GPQ0 (2): SPMI (PMIC I/F)
>>   - GPB0,GPB1,GPB2,GPB3,GPB4,GPB5,GPB6 (47): I2S Audio
>>   - GPH0,GPH1,GPH2,GPH3,GPH4,GPH5,GPH6,GPH8 (49): PCIE, UFS, Ethernet
>>   - GPG0,GPG1,GPG2,GPG3,GPG4,GPG5 (29): General purpose
>>   - GPP0,GPP1,GPP2,GPP3,GPP4,GPP5,GPP6,GPP7,GPP8,GPP9,GPP10 (77): USI
>>
>> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
>> ---
>>   .../pinctrl/samsung/pinctrl-exynos-arm64.c    | 140 ++++++++++++++++++
>>   drivers/pinctrl/samsung/pinctrl-exynos.c      |  23 ++-
>>   drivers/pinctrl/samsung/pinctrl-exynos.h      |  25 ++++
>>   drivers/pinctrl/samsung/pinctrl-samsung.c     |   2 +
>>   drivers/pinctrl/samsung/pinctrl-samsung.h     |   1 +
>>   5 files changed, 190 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
>> index cb965cf93705..a998c296dd05 100644
>> --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
>> +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
>> @@ -796,3 +796,143 @@ const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
>>   	.ctrl		= fsd_pin_ctrl,
>>   	.num_ctrl	= ARRAY_SIZE(fsd_pin_ctrl),
>>   };
>> +
>> +/* pin banks of exynosautov920 pin-controller 0 (ALIVE) */
>> +static const struct samsung_pin_bank_data exynosautov920_pin_banks0[] = {
>> +	EXYNOSV920_PIN_BANK_EINTW(8, 0x0000, "gpa0", 0x18, 0x24, 0x28),
>> +	EXYNOSV920_PIN_BANK_EINTW(2, 0x1000, "gpa1", 0x18, 0x20, 0x24),
>> +	EXYNOS850_PIN_BANK_EINTN(2, 0x2000, "gpq0"),
>> +};e
> Applied with re-ordering it, to keep it after ExynosAutov9. For the
> future: don't add entries to the end of lists because it causes exactly
> this issue we have here: unnecessary conflicts. Please keep this rule
> for entire development, not only pinctrl.
>
> If both you and Peter were observing this basic rule, I would not have
> work of reshuffling and fixing conflicts.
>
> Please check the result if I reshuffled/solved conflicts correctly.
>

I thought the new SoC should go to the end, but I was wrong.

I will follow your comments in alphabetical order.

Thanks you sincerely.


Thanks

Jaewon Kim