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[209.85.219.181]) by smtp.gmail.com with ESMTPSA id f68-20020a0ddc47000000b005d16b6edfffsm4659889ywe.120.2023.12.13.05.43.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Dec 2023 05:43:27 -0800 (PST) Received: by mail-yb1-f181.google.com with SMTP id 3f1490d57ef6-d9b9adaf291so5001821276.1; Wed, 13 Dec 2023 05:43:27 -0800 (PST) X-Received: by 2002:a05:6902:1a45:b0:da0:3b6c:fc22 with SMTP id cy5-20020a0569021a4500b00da03b6cfc22mr3918042ybb.31.1702475006909; Wed, 13 Dec 2023 05:43:26 -0800 (PST) MIME-Version: 1.0 References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> <20231207070700.4156557-5-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20231207070700.4156557-5-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 13 Dec 2023 14:43:16 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 04/11] pinctrl: renesas: rzg2l: Add pin configuration support for pinmux groups To: Claudiu Cc: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 13 Dec 2023 05:43:41 -0800 (PST) Hi Claudiu, On Thu, Dec 7, 2023 at 8:08 AM Claudiu wrote: > From: Claudiu Beznea > > On RZ/G3S different Ethernet pins need to be configured with different > settings (e.g., power-source needs to be set, RGMII TXC and TX_CTL pins > need output-enable). Commit adjust driver to allow specifying pin > configuration for pinmux groups. With this, DT settings like the following > are taken into account by driver: > > eth0_pins: eth0 { > tx_ctl { > pinmux = ; /* ET0_TX_CTL */ > power-source = <1800>; > output-enable; > drive-strength-microamp = <5200>; > }; > }; > > Signed-off-by: Claudiu Beznea > Reviewed-by: Geert Uytterhoeven > --- > > Changes in v2: Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-pinctrl-for-v6.8. > - moved num_configs check under num_pinmux check as suggested Actually my comment was wrong, as I had misunderstood the code flow ("goto done") in case num_pins is non-zero. I will revert to v1 while queuing in renesas-pinctrl-for-v6.8. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds