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[209.85.219.176]) by smtp.gmail.com with ESMTPSA id v187-20020a2548c4000000b00db3fa34142bsm4028960yba.49.2023.12.13.05.46.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Dec 2023 05:46:50 -0800 (PST) Received: by mail-yb1-f176.google.com with SMTP id 3f1490d57ef6-da077db5145so5753183276.0; Wed, 13 Dec 2023 05:46:50 -0800 (PST) X-Received: by 2002:a5b:309:0:b0:db7:dad0:76c8 with SMTP id j9-20020a5b0309000000b00db7dad076c8mr5359241ybp.100.1702475209930; Wed, 13 Dec 2023 05:46:49 -0800 (PST) MIME-Version: 1.0 References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> <20231207070700.4156557-6-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20231207070700.4156557-6-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 13 Dec 2023 14:46:38 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 05/11] pinctrl: renesas: rzg2l: Add support to select power source for Ethernet pins To: Claudiu Cc: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 13 Dec 2023 05:46:58 -0800 (PST) On Thu, Dec 7, 2023 at 8:08 AM Claudiu wrote: > From: Claudiu Beznea > > The GPIO controller available on RZ/G3S (but also on RZ/G2L) allows setting > the power source for Ethernet pins. Based on the interface b/w the Ethernet > controller and the Ethernet PHY and board design specific power source need > to be selected. The GPIO controller allows 1.8V, 2.5V and 3.3V power source > selection for Ethernet pins. This could be selected though ETHX_POC > registers (X={0, 1}). > > Commit adjust the driver to support this and does proper instantiation for > RZ/G3S and RZ/G2L SoC. On RZ/G2L only get operation has been tested at the > moment. > > While at it, as the power registers on RZ/G2L support access sizes of 8 > bits and RZ/G3S support access sizes of 8/16/32 bits, changed > writel()/readl() on these registers with writeb()/readb(). This should > allow using the same code for both SoCs w/o any issues. > > Signed-off-by: Claudiu Beznea > --- > > Changes in v2: > - removed PVDD_MASK > - use 8 bit helpers to get/set value of power register > - replaced if/else with switch/case everywhere Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-pinctrl-for-v6.8. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds