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[211.75.219.200]) by smtp.gmail.com with ESMTPSA id q5-20020a170902bd8500b001c9d011581dsm10531995pls.164.2023.12.13.05.51.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 05:51:26 -0800 (PST) Date: Wed, 13 Dec 2023 21:51:19 +0800 From: Leo Yan To: "Liang, Kan" Cc: acme@kernel.org, irogers@google.com, peterz@infradead.org, mingo@redhat.com, namhyung@kernel.org, jolsa@kernel.org, adrian.hunter@intel.com, john.g.garry@oracle.com, will@kernel.org, james.clark@arm.com, mike.leach@linaro.org, yuhaixin.yhx@linux.alibaba.com, renyu.zj@linux.alibaba.com, tmricht@linux.ibm.com, ravi.bangoria@amd.com, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH V2 4/5] perf mem: Clean up perf_mem_event__supported() Message-ID: <20231213134911.GB3895246@leoy-yangtze.lan> References: <20231207192338.400336-1-kan.liang@linux.intel.com> <20231207192338.400336-5-kan.liang@linux.intel.com> <20231209061723.GC2116834@leoy-yangtze.lan> <2865c1b4-a003-44df-a734-1e1c90bfa14d@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2865c1b4-a003-44df-a734-1e1c90bfa14d@linux.intel.com> X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 13 Dec 2023 05:54:38 -0800 (PST) On Mon, Dec 11, 2023 at 01:44:54PM -0500, Liang, Kan wrote: > > > On 2023-12-09 1:17 a.m., Leo Yan wrote: > > On Thu, Dec 07, 2023 at 11:23:37AM -0800, kan.liang@linux.intel.com wrote: > >> From: Kan Liang > >> > >> For some ARCHs, e.g., ARM and AMD, to get the availability of the > >> mem-events, perf checks the existence of a specific PMU. For the other > >> ARCHs, e.g., Intel and Power, perf has to check the existence of some > >> specific events. > >> > >> The current perf only iterates the mem-events-supported PMUs. It's not > >> required to check the existence of a specific PMU anymore. > > > > With this change, both Arm and AMD archs have no chance to detect if the > > hardware (or the device driver) is supported and the tool will always > > take the memory events are exited on the system, right? > > Currently, the Arm and AMD only check the specific PMU. If the PMU is > detected, the memory events are supported. The patch set doesn't change > it. It just moves the check to perf_pmu__arch_init(). When the specific > PMU is initialized, the mem_events is assigned. You don't need to do > runtime sysfs check. It should be an improvement for ARM and AMD. Okay, I understand now. For Arm SPE, it has a dedicated PMU so if the PMU is detected, then we can assume the memory events are supported. For other cases, you need to check furthermore if PMU has supported specific memory events. This patch is fine for me, you could ignore my comment for the regression caused by this patch. Thanks, Leo