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[209.85.128.174]) by smtp.gmail.com with ESMTPSA id i129-20020a0dc687000000b005463e45458bsm4678994ywd.123.2023.12.13.05.56.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 13 Dec 2023 05:56:32 -0800 (PST) Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-5e248b40c97so14194527b3.2; Wed, 13 Dec 2023 05:56:32 -0800 (PST) X-Received: by 2002:a81:df0f:0:b0:5d7:1940:f3cf with SMTP id c15-20020a81df0f000000b005d71940f3cfmr5689752ywn.55.1702475792558; Wed, 13 Dec 2023 05:56:32 -0800 (PST) MIME-Version: 1.0 References: <20231207070700.4156557-1-claudiu.beznea.uj@bp.renesas.com> <20231207070700.4156557-7-claudiu.beznea.uj@bp.renesas.com> In-Reply-To: <20231207070700.4156557-7-claudiu.beznea.uj@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 13 Dec 2023 14:56:21 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 06/11] pinctrl: renesas: rzg2l: Add output enable support To: Claudiu Cc: s.shtylyov@omp.ru, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, linus.walleij@linaro.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, linux-renesas-soc@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Claudiu Beznea Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 13 Dec 2023 05:58:18 -0800 (PST) On Thu, Dec 7, 2023 at 8:08 AM Claudiu wrote: > From: Claudiu Beznea > > Some of the Ethernet pins on RZ/G3S (but also valid for RZ/G2L) need to > have the direction of the IO buffer set as output for Ethernet to work > properly. On RZ/G3S, these pins are P1_0/P7_0, P1_1/P7_1 which could have > the following Ethernet functions: TXC/TX_CLK or TX_CTL/TX_EN. > > As the pins supporting output enable are SoC specific and there is a > limited number of these pins (TXC/TX_CLK and/or TX_CTL/TX_EN), for proper > validation the output enable capable port limits were specified on > platform-based configuration data structure. > > The OEN support has been intantiated for RZ/G3S at the moment. > > Signed-off-by: Claudiu Beznea > --- > > Changes in v2: > - use 8 bit helpers to get/set value of output enable register > - adapted to code to work for both RZ/G2L based devices and RZ/G3S > - removed IEN capability for Ethernet pins and added it in a separate > patch (patch 07/12) Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-pinctrl-for-v6.8. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds