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Date:   Wed, 13 Dec 2023 09:53:13 -0400
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc:     linux-kernel@vger.kernel.org, iommu@lists.linux.dev,
        joro@8bytes.org, yi.l.liu@intel.com, kevin.tian@intel.com,
        nicolinc@nvidia.com, eric.auger@redhat.com, vasant.hegde@amd.com,
        jon.grimm@amd.com, santosh.shukla@amd.com, Dhaval.Giani@amd.com,
        pandoh@google.com, loganodell@google.com
Subject: Re: [RFC PATCH 5/6] iommu/amd: Introduce helper functions to setup
 GCR3TRPMode
Message-ID: <20231213135313.GE3259566@nvidia.com>
References: <20231212160139.174229-1-suravee.suthikulpanit@amd.com>
 <20231212160139.174229-6-suravee.suthikulpanit@amd.com>
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On Tue, Dec 12, 2023 at 10:01:38AM -0600, Suravee Suthikulpanit wrote:
> +/*
> + * For GCR3TRPMode, user-space provides GPA for the GCR3 Root Pointer Table.
> + */
> +int amd_iommu_set_gcr3tbl_trp(struct amd_iommu *iommu, struct pci_dev *pdev,
> +			      u64 gcr3_tbl, u16 glx, u16 guest_paging_mode)
> +{
> +	struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev);
> +	struct dev_table_entry *dev_table = get_dev_table(iommu);
> +	struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info;
> +	int devid = pci_dev_id(pdev);
> +	u64 data0 = dev_table[devid].data[0];
> +	u64 data1 = dev_table[devid].data[1];
> +	u64 data2 = dev_table[devid].data[2];
> +	u64 tmp;

Like I said in my other email, this whole function is conceptually
wrong - you can't read the DTE to learn the parent domain's
contribution to the nesting DTE and you can't write to the DTE during
allocation of a domain!

Jason