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Wed, 13 Dec 2023 17:15:29 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3BDHFS8w019171 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 13 Dec 2023 17:15:28 GMT Received: from [10.110.0.246] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 13 Dec 2023 09:15:26 -0800 Message-ID: <7083b139-b6f7-44ed-b294-5c69fceed604@quicinc.com> Date: Wed, 13 Dec 2023 09:15:25 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/panel: ltk050h3146w: Set burst mode for ltk050h3148w Content-Language: en-US To: Farouk Bouabid , , , , , , , , CC: , , , References: <20231213145045.41020-1-farouk.bouabid@theobroma-systems.com> From: Jessica Zhang In-Reply-To: <20231213145045.41020-1-farouk.bouabid@theobroma-systems.com> Content-Type: text/plain; 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Wed, 13 Dec 2023 09:16:09 -0800 (PST) On 12/13/2023 6:50 AM, Farouk Bouabid wrote: > The ltk050h3148w variant expects the horizontal component lane byte clock > cycle(lbcc) to be calculated using lane_mbps (burst mode) instead of the > pixel clock. > Using the pixel clock rate by default for this calculation was introduced > in commit ac87d23694f4 ("drm/bridge: synopsys: dw-mipi-dsi: Use pixel clock > rate to calculate lbcc") and starting from commit 93e82bb4de01 > ("drm/bridge: synopsys: dw-mipi-dsi: Fix hcomponent lbcc for burst mode") > only panels that support burst mode can keep using the lane_mbps. So add > MIPI_DSI_MODE_VIDEO_BURST as part of the mode_flags for the dsi host. > > Fixes: 93e82bb4de01 ("drm/bridge: synopsys: dw-mipi-dsi: Fix hcomponent lbcc for burst mode") > Signed-off-by: Farouk Bouabid Reviewed-by: Jessica Zhang Thanks, Jessica Zhang > --- > drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c b/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c > index 6e3670508e3a..30919c872ac8 100644 > --- a/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c > +++ b/drivers/gpu/drm/panel/panel-leadtek-ltk050h3146w.c > @@ -326,7 +326,7 @@ static const struct drm_display_mode ltk050h3148w_mode = { > static const struct ltk050h3146w_desc ltk050h3148w_data = { > .mode = <k050h3148w_mode, > .init = ltk050h3148w_init_sequence, > - .mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE, > + .mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_VIDEO_BURST, > }; > > static int ltk050h3146w_init_sequence(struct ltk050h3146w *ctx) > -- > 2.34.1 >