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[82.149.12.148]) by smtp.gmail.com with ESMTPSA id m11-20020a056000008b00b0033332524235sm14110534wrx.82.2023.12.13.12.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 13 Dec 2023 12:26:33 -0800 (PST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Paul Kocialkowski Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Maxime Ripard , Laurent Pinchart , Michael Turquette , Stephen Boyd , Paul Kocialkowski Subject: Re: [PATCH v7 7/7] ARM: dts: sun8i-a83t: Add BananaPi M3 OV8865 camera overlay Date: Wed, 13 Dec 2023 21:26:32 +0100 Message-ID: <3780932.kQq0lBPeGt@archlinux> In-Reply-To: <20231122141426.329694-8-paul.kocialkowski@bootlin.com> References: <20231122141426.329694-1-paul.kocialkowski@bootlin.com> <20231122141426.329694-8-paul.kocialkowski@bootlin.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="iso-8859-1" X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 13 Dec 2023 12:26:45 -0800 (PST) Hi Paul, same comments as for patch 6. Best regards, Jernej On Wednesday, November 22, 2023 3:14:25 PM CET Paul Kocialkowski wrote: > Add an overlay supporting the OV8865 from the BananaPi Camera v3 > peripheral board. The board has two sensors (OV5640 and OV8865) > which cannot be supported in parallel as they share the same reset > pin and the kernel currently has no support for this case. >=20 > Signed-off-by: Paul Kocialkowski > --- > arch/arm/boot/dts/allwinner/Makefile | 1 + > .../sun8i-a83t-bananapi-m3-camera-ov8865.dtso | 109 ++++++++++++++++++ > 2 files changed, 110 insertions(+) > create mode 100644 arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-ca= mera-ov8865.dtso >=20 > diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/all= winner/Makefile > index a0a9aa6595e4..980ac88634e3 100644 > --- a/arch/arm/boot/dts/allwinner/Makefile > +++ b/arch/arm/boot/dts/allwinner/Makefile > @@ -278,6 +278,7 @@ dtb-$(CONFIG_MACH_SUN8I) +=3D \ > sun8i-a83t-allwinner-h8homlet-v2.dtb \ > sun8i-a83t-bananapi-m3.dtb \ > sun8i-a83t-bananapi-m3-camera-ov5640.dtbo \ > + sun8i-a83t-bananapi-m3-camera-ov8865.dtbo \ > sun8i-a83t-cubietruck-plus.dtb \ > sun8i-a83t-tbs-a711.dtb \ > sun8i-h2-plus-bananapi-m2-zero.dtb \ > diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov= 8865.dtso b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov886= 5.dtso > new file mode 100644 > index 000000000000..0656ee8d4bfe > --- /dev/null > +++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3-camera-ov8865.dt= so > @@ -0,0 +1,109 @@ > +// SPDX-License-Identifier: GPL-2.0 OR X11 > +/* > + * Copyright 2022 Bootlin > + * Author: K=E9vin L'h=F4pital > + * Author: Paul Kocialkowski > + */ > + > +/dts-v1/; > +/plugin/; > + > +#include > +#include > + > +&{/} { > + /* > + * These regulators actually have DLDO4 tied to their EN pin, which is > + * described as input supply here for lack of a better representation. > + * Their actual supply is PS, which is always-on. > + */ > + > + ov8865_avdd: ov8865-avdd { > + compatible =3D "regulator-fixed"; > + regulator-name =3D "ov8865-avdd"; > + regulator-min-microvolt =3D <2800000>; > + regulator-max-microvolt =3D <2800000>; > + vin-supply =3D <®_dldo4>; > + }; > + > + ov8865_dovdd: ov8865-dovdd { > + compatible =3D "regulator-fixed"; > + regulator-name =3D "ov8865-dovdd"; > + regulator-min-microvolt =3D <2800000>; > + regulator-max-microvolt =3D <2800000>; > + vin-supply =3D <®_dldo4>; > + }; > + > + ov8865_dvdd: ov8865-dvdd { > + compatible =3D "regulator-fixed"; > + regulator-name =3D "ov8865-dvdd"; > + regulator-min-microvolt =3D <1200000>; > + regulator-max-microvolt =3D <1200000>; > + vin-supply =3D <®_dldo4>; > + }; > +}; > + > +&ccu { > + assigned-clocks =3D <&ccu CLK_CSI_MCLK>; > + assigned-clock-parents =3D <&osc24M>; > + assigned-clock-rates =3D <24000000>; > +}; > + > +&csi { > + status =3D "okay"; > +}; > + > +&i2c2 { > + pinctrl-names =3D "default"; > + pinctrl-0 =3D <&i2c2_pe_pins>; > + status =3D "okay"; > + > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + ov8865: camera@36 { > + compatible =3D "ovti,ov8865"; > + reg =3D <0x36>; > + > + clocks =3D <&ccu CLK_CSI_MCLK>; > + assigned-clocks =3D <&ccu CLK_CSI_MCLK>; > + assigned-clock-parents =3D <&osc24M>; > + assigned-clock-rates =3D <24000000>; > + > + avdd-supply =3D <&ov8865_avdd>; > + dovdd-supply =3D <&ov8865_dovdd>; > + dvdd-supply =3D <&ov8865_dvdd>; > + > + powerdown-gpios =3D <&pio 4 17 GPIO_ACTIVE_LOW>; /* PE17 */ > + reset-gpios =3D <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */ > + > + port { > + ov8865_out_mipi_csi2: endpoint { > + remote-endpoint =3D <&mipi_csi2_in_ov8865>; > + link-frequencies =3D /bits/ 64 <360000000>; > + data-lanes =3D <1 2 3 4>; > + }; > + }; > + }; > +}; > + > +&mipi_csi2 { > + status =3D "okay"; > +}; > + > +&mipi_csi2_in { > + mipi_csi2_in_ov8865: endpoint { > + remote-endpoint =3D <&ov8865_out_mipi_csi2>; > + data-lanes =3D <1 2 3 4>; > + }; > +}; > + > +&pio { > + pinctrl-names =3D "default"; > + pinctrl-0 =3D <&csi_mclk_pin>; > +}; > + > +®_dldo4 { > + regulator-min-microvolt =3D <2800000>; > + regulator-max-microvolt =3D <2800000>; > +}; >=20